gEDA-user: iverilog from simulation to xnf

[gtodd@mail.utexas.edu]

Hello,

     I am writing verilog code to program a xiling xc4005xl to perform a fairly 
complex mathematical formula.   Using icarus verilog (v_0_6_1) to compile and 
simulate the code I have, so far, works fine.  Using $display, and compiling my 
code 'iverilog -omath math.v', './math' does just what I want it to.

     Now, when attempting to generate a xilinx netlist formatted file with the 
same code ('iverilog -txnf math.v' or similar 'iverilog -txnf -fcnf=math.cnf 
math.v') generates the following errors:

-- BEGIN ERROR

NetBlock::match_proc
default (failing) match for block
NetBlock::match_proc
default (failing) match for block
target (10target_xnf): Unhandled task definition.
target (10target_xnf): Unhandled task definition.
target (10target_xnf): Unhandled task definition.
target (10target_xnf): Unhandled task definition.
target (10target_xnf): Unhandled proc_block.
error: Code generation had errors.

-- END ERROR

These errors are somewhat vague to me.  Especially considering that they look 
like syntactical errors, which is frustrating considering that it compiles fine.

My verilog code is fairly simple and consists of four tasks, each with atleast 
one defined input.  The main module also consists of atleast one input.  

I am fairly confused as to why the simulation and compilation works fine, but 
the same code will error out when attempting to created a XNF.

Any help, or points of reference (I have read through verilog/xnf.txt), is 
greatly appreciated.

Cheers