Re: gEDA-user: iverilog from simulation to xnf

[Stephen Williams <steve@icarus.com>]

adyer@enteract.com said:
> I don't believe tasks are generally included in the synthesizable
> subset of verilog.  If you need tasks for simulation and testbench
> stuff that's usually put in a testbench file which doesn't get
> inlcuded when synthesizing.

There's nothing about tasks that makes them inherently not
synthesizeable, but I bet there aren't many Verilog synthesizers
that go through the lifetime analysis needed to do the job.  In
any case, Icarus Verilog can't do synthesis on tasks, and a few
other things in the sample, judging from the error messages.

On Tue, May 14, 2002 at 07:07:32PM -0500, gtodd@mail.utexas.edu wrote:
> These errors are somewhat vague to me.  Especially considering that they look 
> like syntactical errors, which is frustrating considering that it compiles fine.

They are vague. They are basically saying, though, that the not-very-
advanced synthesizer in Icarus Verilog doesn't know what to do with a
bunch of things in your program. Remember that compilation for simulation
is very different from synthesis, and Icarus Verilog synthesis is not
at all complete or exhaustive. I'm working on it:-)
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

abuse@xo.com
uce@ftc.gov