Re: gEDA-user: debugger for verilog

[Matthew Ballance <ballance@ballance.dhs.org>]

Hi,
    I'm working on a way to do this. The project is called IVI (Icarus
Verilog Interactive). Currently, it doesn't support single-stepping
through a verilog simulation, but that is planned. At the moment, it
supports loading a verilog design, simulating the design, and viewing
the waveforms from the simulation in real time.
    The project's homepage is http://ivi.sourceforge.net . This is just
for future reference, as there isn't much up there right now...
    A pre-alpha version of IVI will probably be released sometime in the
next two months...

Regards,
Matt


On Sun, 2002-05-26 at 13:18, Jim Sytniak wrote:
> Is there a way to debug/single step thru verilog source possibly based on the compiled output of Iverilog? Maybe GDB can be configured to do this???