Re: gEDA-user: debugger for verilog

[Stephen Williams <steve@icarus.com>]

ballance@ballance.dhs.org said:
> I'm working on a way to do this. The project is called IVI (Icarus
> Verilog Interactive). Currently, it doesn't support single-stepping
> through a verilog simulation, but that is planned. At the moment, it
> supports loading a verilog design, simulating the design, and viewing
> the waveforms from the simulation in real time.

Will it be possible to input waveforms and generate test benches
from that? It should even be possible to poke and prod bits using
vpi_put_value.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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