Re: gEDA-user: debugger for verilog

[Matthew Ballance <ballance@ballance.dhs.org>]

Hi Steve,
   Are you planning to support vpiDefLineNo and vpiDefFile soon? This
functionality, obviously, is rather key for support of a symbolic
debugger. I've looked at the issue and it seems to be mainly an issue of
making line number and file information available to the target API. As
far as I can see, line/file info is available up to the elaborate stage.
   If you aren't planning to do this for some time, then I'll probably
dig in and do the work. Otherwise, it makes much more sense for you to
do the work since you're more familiar with the IVL core. If you don't
plan to do the work, have you any pointers for me?

Thanks,
Matt

On Sun, 2002-05-26 at 16:27, Stephen Williams wrote:
> 
> ballance@ballance.dhs.org said:
> > I'm working on a way to do this. The project is called IVI (Icarus
> > Verilog Interactive). Currently, it doesn't support single-stepping
> > through a verilog simulation, but that is planned. At the moment, it
> > supports loading a verilog design, simulating the design, and viewing
> > the waveforms from the simulation in real time.
> 
> Will it be possible to input waveforms and generate test benches
> from that? It should even be possible to poke and prod bits using
> vpi_put_value.
> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
> 
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