Re: gEDA-user: debugger for verilog

[Matthew Ballance <ballance@ballance.dhs.org>]

On Sun, 2002-05-26 at 16:27, Stephen Williams wrote:
> 
> ballance@ballance.dhs.org said:
> > I'm working on a way to do this. The project is called IVI (Icarus
> > Verilog Interactive). Currently, it doesn't support single-stepping
> > through a verilog simulation, but that is planned. At the moment, it
> > supports loading a verilog design, simulating the design, and viewing
> > the waveforms from the simulation in real time.
> 

> Will it be possible to input waveforms and generate test benches
> from that? It should even be possible to poke and prod bits using
> vpi_put_value.

Yes, that should be possible. IVI is TCL-based, so testbenches can be
created using a TCL script. It currently isn't possible to create/edit
waveforms interactively using the waveform viewer. That is certainly
something that I'll look into for the future.

-Matt


> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
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