Re: gEDA-user: draw_binary_real??

["cfk" <cfk@pacbell.net>]

Dear Stephen:
    What I did was to untar the ethernet.tar.gz file to its default ethernet
directory. Next, I went into that directory and made a net directory where I
copied all of the .v files from ethernet/bench/verilog and
ethernet/rtl/verilog. Next, I edited tb_ethernet.v to `include all of the .v
files instantiated in the bench. Next, I changed the 8 or so occurences of
phy_data assignment to +1'd1 from +1. Similarly there were two lines similar
in wb_bus_mon.v. At that point, I could go 'iverilog tb_ethernet.v' and get
the draw_binary_real assertion.

    I have since our last e-mail been looking for draw_binary_real and
eval_real somewhat unsuccessfully with kdevelop's find in files (usually
works just fine and that puzzles me).

    Additionally, I have started trying to compile the .v's individually. I
can compile wb_bus_mon.v with no assertions, but the second one
wb_master32.v comes back with:
    ivl:eval_tree.cc:303: NetEConst* NetEBComp::eval_gt_(): Assertion
'right_->exptr_width() > 0' failed

which itself is kinda interesting.

    Anyway, the long winded answer is no command file, I just added the
module names as includes in tb_ethernet.v (took about 5 minutes).


----- Original Message -----
From: "Stephen Williams" <steve@icarus.com>
To: <geda-user@seul.org>
Sent: Friday, May 23, 2003 8:14 PM
Subject: Re: gEDA-user: draw_binary_real??


>
> cfk@pacbell.net said:
> > Sure, just go to http://www.opencores.org and download the ethernet
> > project, expand it, go to the bench directory, correct the 8'd1 issue
> > in tb_ethernet.v and compile with iverilog.
>
> You have a command file that can compile the whole simulation?
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>