Re: gEDA-user: draw_binary_real??

["cfk" <cfk@pacbell.net>]

Dear Stephen:
    I am not dissing iverilog in the slightest, but I do want to urge you to
consider a couple of things.

    I have tried unsuccessfully to synthesize both the pci and the ethernet
projects from opencore and in both cases, I have been stopped by iverilog
throwing an assertion. This latest one with draw_binary_real appears to me
to be a case of the draw_binary_real function in tgt-vvp getting an
ivl_expr_opcode that is neither add, sub or mul and the default case throws
the assertion when that happens.

    I believe there is some logical expression in the code given to iverilog
by the ethernet project that causes this, but I would argue that the
synthesizer should then provide some message that allows the user to figure
out what's wrong. I can imagine that this late in the synthesis, it may be
difficult to point to a file and line number, but nonetheless, the
synthesizer (or compiler, for C for that matter), should say *something*
that gives a clue.

    It could be as clear as "syntax error, missing ; at line 357", or even
as obscure as "no rule to make target file x" from make, but nonetheless,
some clue is given that allows the user to figure out what is going on.

    Iverilog works fine with small verilog source files. But the issue seems
to be with larger projects. As projects get more complex, and users take
others cores (such as the ethernet or pci cores from opencores.org), it
seems very important to me that the synthesis tool allows a solution to
converge.

    Your patch is very appreciated and very interesting, but I think the
more important issue here is that iverilog would be much more useful it if
did not throw assertions with faulty verilog input, but rather gave some
clue that allowed the user to converge on what is wrong.

    Again, this is not a flame, I am trying to suggest a way to make your
wonderful tool more useful

Charles Krinke


----- Original Message -----
From: "Stephen Williams" <steve@icarus.com>
To: <geda-user@seul.org>
Sent: Friday, May 23, 2003 9:06 PM
Subject: Re: gEDA-user: draw_binary_real??


>
>   XXXX draw_binary_real(%)
>   ivl: eval_real.c:83: draw_binary_real: Assertion '0' failed.
>
> Try the attached patch.
>
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>
> Index: tgt-vvp/eval_real.c
> ===================================================================
> RCS file: /home/u/icarus/steve/CVS/verilog/tgt-vvp/eval_real.c,v
> retrieving revision 1.8
> diff -c -r1.8 eval_real.c
> *** tgt-vvp/eval_real.c 23 Apr 2003 02:22:47 -0000 1.8
> --- tgt-vvp/eval_real.c 24 May 2003 04:05:10 -0000
> ***************
> *** 57,63 ****
>
>   static int draw_binary_real(ivl_expr_t exp)
>   {
> !       int l, r;
>
>         l = draw_eval_real(ivl_expr_oper1(exp));
>         r = draw_eval_real(ivl_expr_oper2(exp));
> --- 57,63 ----
>
>   static int draw_binary_real(ivl_expr_t exp)
>   {
> !       int l, r = -1;
>
>         l = draw_eval_real(ivl_expr_oper1(exp));
>         r = draw_eval_real(ivl_expr_oper2(exp));
> ***************
> *** 80,91 ****
>       fprintf(vvp_out, "    %%div/wr %d, %d;\n", l, r);
>       break;
>
>     default:
>       fprintf(stderr, "XXXX draw_binary_real(%c)\n",
>       ivl_expr_opcode(exp));
>       assert(0);
>         }
> !       clr_word(r);
>
>         return l;
>   }
> --- 80,102 ----
>       fprintf(vvp_out, "    %%div/wr %d, %d;\n", l, r);
>       break;
>
> +   case '%':
> +       { struct vector_info res = draw_eval_expr(exp, STUFF_OK_XZ);
> + l = allocate_word();
> + fprintf(vvp_out, "    %%ix/get %d, %u, %u;\n",
> + l, res.base, res.wid);
> + fprintf(vvp_out, "    %%cvt/ri %d, %d;\n", l, l);
> +         clr_vector(res);
> +       }
> +       break;
> +
>     default:
>       fprintf(stderr, "XXXX draw_binary_real(%c)\n",
>       ivl_expr_opcode(exp));
>       assert(0);
>         }
> !
> !       if (r >= 0) clr_word(r);
>
>         return l;
>   }
>