gEDA-user: Anyone have any success with Icarus Verilog and Altera's Quartus software?

[Charles Lepple <clepple@ghz.cc>]

I'm evaluating Altera's Quartus II software (roughly same capabilities 
as Xilinx's Webpack) and I was wondering if anyone had done any 
successful P+R in Quartus with the EDIF output of Icarus Verilog.

I realize there are some missing pieces to map generic EDIF to what 
Quartus is expecting, and I think what Quartus needs is a "mapping 
file" (this is from memory; I don't have Quartus available here at 
home). Tips from anyone who has been down this road before would be 
greatly appreciated.

I was going to just use Quartus' synthesis engine, but it chokes on 
some simple OpenCores modules (dpram, plus the oc8051 ROM).

Also, has anyone tried to use the tgt-edif code? Info here:

http://volodya-project.sourceforge.net/tgt-edif.php

The comments and latest CVS entries are nearly two years old. Given all 
of the synthesis improvements in iverilog since then, I would be 
surprised if it dropped right in, but I am interested to hear if anyone 
else has tried it.

--
Charles Lepple <clepple@ghz.cc>
http://www.ghz.cc/charles/