gEDA-user: verilog real input and output

["David Ward" <dward@xxxxxxxxxxxx>]

I am trying to do the following input and output with a verilog module in icarus verilog.

 

Icarus complains that the output is already defined as a wire so I’m guessing you cannot do real outputs.  I would like to use the tool to model very simple analog functions.

 

Any help or ideas would be appreciated.

 

module passreal (vin,out);

input vin;

output out;

real vin;

real out;

 

always begin

            #1;

            out = vin * 2;

end

 

endmodule

 

Thanks,

dave