Re: gEDA-user: iverilog EDIF VCC/GND references?

[Stephen Williams <steve@xxxxxxxxxx>]

Harold D. Skank wrote:
> People,
>
> I'm trying to get an EDIF file generated by iverilog-fpga transferred to
> a Lattice package (ispLEVER, Version 4.2 - Linux).  It appears that the
> Lattice package needs to know how iverilog handled the VCC and GND
> references in the design.  Looking at the EDIF file, I would suppose
> that the GND references were denoted by "cell0" and that the VCC
> references were denoted by "cell1".  Is this correct, and if not, what
> should they be?

I *think* it should have generated the proper cell declarations
for VCC and GND. Even Xilinx tools expect a declaration for all
including VCC and GND cells, so they should be there.

--
Steve Williams                "The woods are lovely, dark and deep.
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