[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

gEDA-user: iverilog EDIF VCC/GND references?

To: geda-user@xxxxxxxx
Subject: gEDA-user: iverilog EDIF VCC/GND references?
From: "Harold D. Skank" <skank54@xxxxxxxxx>
Date: Tue, 10 May 2005 11:04:06 -0500
Cc: "Skank, Harold" <skank54@xxxxxxxxx>
Delivered-to: archiver@seul.org
Delivered-to: geda-user-outgoing@seul.org
Delivered-to: geda-user@seul.org
Delivery-date: Tue, 10 May 2005 12:02:17 -0400
Reply-to: geda-user@xxxxxxxx
Sender: owner-geda-user@xxxxxxxx

People,

I'm trying to get an EDIF file generated by iverilog-fpga transferred to
a Lattice package (ispLEVER, Version 4.2 - Linux).  It appears that the
Lattice package needs to know how iverilog handled the VCC and GND
references in the design.  Looking at the EDIF file, I would suppose
that the GND references were denoted by "cell0" and that the VCC
references were denoted by "cell1".  Is this correct, and if not, what
should they be?

	Harold Skank

Follow-Ups:
- Re: gEDA-user: iverilog EDIF VCC/GND references?
  - From: Stephen Williams

Prev by Author: Re: gEDA-user: Problems with gnetlist -g verilog for vector signals?
Next by Author: gEDA-user: cell0 and cell1 references in EDIF file?
Previous by thread: Re: gEDA-user: pcb question : same structure several times on board
Next by thread: Re: gEDA-user: iverilog EDIF VCC/GND references?
Index(es):
- Author
- Thread