Re: gEDA-user: Problems with gnetlist -g verilog for vector signals?

["Harold D. Skank" <skank54@xxxxxxxxx>]

Sir;

I appreciate your information and explanation, however I have been here
before in connection with Xilinx chips running under Cadence Concept.
The eventual outcome is that by the time you have to do the chip
fabrication you can't use vectored notation at the pin level anyway.
You have to account for each pin individually.  So, I guess in the long
run this becomes a "non-issue".  Even though vector notation would be
nice at the test level, I really don't want to do everything twice.

Thanks much.

	Harold Skank

On Fri, 2005-05-06 at 10:03 -0400, Mike Jarabek wrote:
> Hi, 
> 
> "Harold D. Skank" wrote: 
> > 
> > People, 
> > 
> > I'm trying to use Icarus Verilog for some chip generation I'm
> > doing. 
> > That package seems to be working fine, but trying to generate a
> > netlist 
> > using gnetlist -g verilog ---- on a schematic which used vector
> > notation 
> > on signals seems to generate multiple declarations of the vectored
> > input 
> > and output signals without the vector reference.  Is this a common 
> > problem, or am I doing something wrong?
> > 
> This is because `bus' pins don't exist in gschem. I had to use a trick
> to handle verilog vectors.  I scan the list of nets in the design and
> extract the high and low indices.  I also scan the order of the
> indices from each of the nets to decide whether the LSB has the higher
> or lower index.  I use this table to generate the wire declaration
> section in the header. 
> 
> Verilog does not allow named module ports to have part selects on
> them, but it's nice to see the width on the schematic.  So I decided
> that port names should be instantiated without any vector notation.
> That is, I srip off the `[  ]' from the end of the signal. 
> 
> If you wish to connect a verilog vector to a port on a symbol, simply
> create a single port on the symbol with the name you want with or
> without the vector notaion, e.g. don't create n ports on the symbol
> for n bits in the vector.  If the signal represents a vector with the
> right width then just connect a net with the right name to the port.
> If you only want a part of the vector, then use a short net segment
> named with the appropriate part select. e.g NET[5:3].  This will
> likely generate what you want.  If you want some extra eye candy in
> your schematic you can use the `bus' drawing function and connect
> small net segments using the bus rippers. 
> 
> Some examples: 
> 
> A net named                 ->  Connected to a port named    : Results
> in 
> MYNET                         ->
> MYPORT                                    :  .MYPORT(MYNET) 
> MYNET                         ->  MYPORT
> [31:0]                         :  .MYPORT(MYNET) 
> MYNET[31:0]              ->  MYPORT
> [31:0]                        : .MYPORT(MYNET[31:0]) 
> 
> A final note, if you wish to concatenate several signals into one
> signal to be fed to a vectored port, you will have to create a special
> symbol and underlying verilog module that provides the concatenation.
> That is, I don't support Verilog's `{   }' notation in the netlister
> directly.  You would have to do this if the bit range to be connected
> was not a simple integer range of bits, but had `holes' in it. 
> 
> A final note about ports for the module being designed, I usually add
> the full vector width to the net connected to the port symbol (IPAD,
> OPAD, IOPAD) to ensure that the netlister sees the full width
> somewhere on the diagram. 
> 
> Hope this helps. 
> 
> Mike 
> > 
> >   
> > 
> > As far as I can tell, scaler signal references netlist OK. 
> > 
> >         Harold Skank
> > 
> -- 
> --------------------------------------------------
>                               Mike Jarabek        
>                                 FPGA/ASIC Designer
>   http://www.istop.com/~mjarabek                    
> --------------------------------------------------
>