Sir;I am a bit confused by your statement about doing everything twice. Doesn't the synthesiser you are using take care of most of that anyhow?I appreciate your information and explanation, however I have been here
before in connection with Xilinx chips running under Cadence Concept.
The eventual outcome is that by the time you have to do the chip
fabrication you can't use vectored notation at the pin level anyway.
You have to account for each pin individually. So, I guess in the long
run this becomes a "non-issue". Even though vector notation would be
nice at the test level, I really don't want to do everything twice.
Can you post an example of how you might like vectored ports to be handled? Perhaps we can arrive at something that will work. What would be your ideal behaviour? Any ideas about how to handle errors?
Mike
-- -------------------------------------------------- Mike Jarabek FPGA/ASIC Designer http://www.istop.com/~mjarabek --------------------------------------------------