Re: gEDA-user: Problems with gnetlist -g verilog for vectorsignals?

[John Sheahan <jrsheahan@xxxxxxxxxxxxxxxx>]

Its pretty common to burst busses for both asic and fpga pinouts.
Tools I have used for that dislike busses.

If your very top level has to use a burst bus, where is the best place
in the design representation to do it?

regards, John



Mike Jarabek wrote:

> I am a bit confused by your statement about doing everything twice.  
> Doesn't the synthesiser you are using take care of most of that anyhow?
>
> Can you post an example of how you might like vectored ports to be 
> handled?  Perhaps we can arrive at something that will work.  What would 
> be your ideal behaviour? Any ideas about how to handle errors?
>
> Mike