People, I need some help here! I'm using iverilog to provide simulation capability, and to generate an EDIF design file to submit to a Lattice Semiconductor package for place and route. Everything seems to go OK up to the submission of the EDIF file, at which point the Lattice package doesn't seem to understand reference to "cell0" and "cell1". Frankly, looking at the EDIF file, I don't understand them either. I should explain that in generating the schematics I have used custom generated (by myself) symbols that call Lattice's verilog library. I finally figured out that I needed to use the ipad-1.sym and opad-1.sym symbols from the gEDA verilog library to which I added the high-1.sym and low-1.sym elements. The ipad and opad references apparently permit iverilog to recognize and properly instantiate the input and output ports while the high and low references wind up generating "assign <netname> 1'b1;" and "assign <netname> 1'b0;" statements respectively. At this point I was able to generate and simulate pretty much an entire chip successfully. Problems began to occur following the iverilog-fpga call which generated the EDIF file that I submitted to the Lattice compiler. To help understand things without the clutter of my own design issues, I have generated a very simple circuit. Attached you will find copies of the postscript output from gEDA gschem, the test.v file generated by iverilog -t vvp, and the final test.edn file generated by iverilog -t fpga. I would appreciate it if someone could look at these files and tell me what the references to cell0 and cell1 represent. In this example, please note that the EDIF file contains references to both these entities, however only cell1 appears to have an associated net. Hoping for some understanding. Regards, Harold Skank
Attachment:
test.ps
Description: PostScript document
/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
/* Id ..........$Id: gnet-verilog.scm,v 1.14 2005/02/03 12:49:36 danmc Exp $ */
/* Source.......$Source: /home/cvspsrv/cvsroot/eda/geda/devel/gnetlist/scheme/gnet-verilog.scm,v $ */
/* Revision.....$Revision: 1.14 $ */
/* Author.......$Author: danmc $ */
module TEST (
TstOut
);
/* Port directions begin here */
output TstOut ;
/* Wires from the design */
wire TstOut ;
wire unnamed_net1 ;
/* continuous assignments */
assign unnamed_net1 = 1'b1;
/* Package instantiations */
OB11 U3 (
.A0 ( unnamed_net1 ),
.XO0 ( TstOut )
);
endmodule
(edif TEST
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 0 0 0 0 0 0)
(author "unknown")
(program "Icarus Verilog/fpga.tgt")))
(external LPM_LIBRARY (edifLevel 0) (technology (numberDefinition))
(cell cell1 (cellType GENERIC)
(view net
(viewType NETLIST)
(interface
(port Result0 (direction OUTPUT))
(property LPM_CValue (integer 1))
(property LPM_Width (integer 1))
(property LPM_Type (string "LPM_CONSTANT")))))
(cell cell0 (cellType GENERIC)
(view net
(viewType NETLIST)
(interface
(port Result0 (direction OUTPUT))
(property LPM_CValue (integer 0))
(property LPM_Width (integer 1))
(property LPM_Type (string "LPM_CONSTANT")))))
(cell BUF (cellType GENERIC)
(view net
(viewType NETLIST)
(interface
(port Result (direction OUTPUT) (property LPM_Polarity (string "INVERT")))
(port Data (direction INPUT))
(property LPM_Size (integer 1))
(property LPM_Width (integer 1))
(property LPM_TYPE (string "LPM_INV")))))
)
(library DESIGN
(edifLevel 0)
(technology (numberDefinition))
(cell TEST
(cellType GENERIC)
(view net
(viewType NETLIST)
(interface
(port TstOut (direction OUTPUT))
)
(contents
(instance U2 (viewRef net (cellRef cell1 (libraryRef LPM_LIBRARY))))
(instance U1 (viewRef net (cellRef BUF (libraryRef LPM_LIBRARY))))
(net N0 (joined (portRef Result0 (instanceRef U2)) (portRef Data (instanceRef U1))))
(net N1 (joined (portRef Result (instanceRef U1)) (portRef TstOut)))
)
)
)
)
(design TEST
(cellRef TEST (libraryRef DESIGN))
)
)