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Re: gEDA-user: New PostScript back-end checked in

To: geda-user@xxxxxxxx
Subject: Re: gEDA-user: New PostScript back-end checked in
From: David Carr <dc@xxxxxxxxx>
Date: Fri, 19 May 2006 02:41:07 -0500
Delivered-to: archiver@seul.org
Delivered-to: geda-user-outgoing@seul.org
Delivered-to: geda-user@seul.org
Delivery-date: Fri, 19 May 2006 03:41:15 -0400
In-reply-to: <1147955126.26873.24.camel@laptop>
References: <1147919998.26873.21.camel@laptop> <446C0029.9010109@dcarr.org> <1147955126.26873.24.camel@laptop>
Reply-to: geda-user@xxxxxxxx
Sender: owner-geda-user@xxxxxxxx
User-agent: Mail/News 1.5 (X11/20060309)

Mike,

I just updated libgeda and rebuilt gschem too for good measure. Now when I print I can't get ggv to show anything (just a blank page). I've attached the postscript output and the original schematic.

Thanks,
David Carr

Mike Jarabek wrote:

On Thu, 2006-05-18 at 00:03 -0500, David Carr wrote:
Mike,
I got: make[2]: Entering directory `/home/david/Desktop/geda/devel/libgeda/share' make[2]: *** No rule to make target `prolog.ps', needed by `all-am'. Stop. make[2]: Leaving directory `/home/david/Desktop/geda/devel/libgeda/share'
Touche... The missing bit is in CVS now.  Sorry about that.
when I tried to compile the new version...
Should work better after a cvs update.
Mike

v 20060123 1
C 69800 34700 0 0 0 title-bordered-subD.sym
T 90800 35600 9 10 1 0 0 0 1
DSO-1 - SODIMM
T 94800 35300 9 10 1 0 0 0 1
V0.1
T 94900 35000 9 10 1 0 0 0 1
(C) David Carr 2006
C 82700 39100 1 0 0 sodimm144.sym
{
T 83784 54080 5 10 1 1 0 6 1
refdes=J?
}
C 85200 38700 1 0 0 gnd-1.sym
C 82300 38700 1 0 0 gnd-1.sym
N 84900 39800 85300 39800 4
N 84900 41800 85300 41800 4
N 84900 43000 85300 43000 4
N 84900 44600 85300 44600 4
N 84900 46200 85300 46200 4
N 84900 48200 85300 48200 4
N 84900 53600 85300 53600 4
N 85300 39000 85300 53600 4
N 84900 51600 85300 51600 4
N 84900 50200 85300 50200 4
N 82800 39800 82400 39800 4
N 82800 41800 82400 41800 4
N 82800 43000 82400 43000 4
N 82800 44600 82400 44600 4
N 82800 46200 82400 46200 4
N 82800 48200 82400 48200 4
N 82800 53600 82400 53600 4
N 82800 51600 82400 51600 4
N 82800 50200 82400 50200 4
N 82400 39000 82400 53600 4
C 82000 53900 1 0 0 3.3V-plus-1.sym
N 82200 52600 82800 52600 4
N 82800 51000 82200 51000 4
N 82800 49200 82200 49200 4
N 82800 47400 82200 47400 4
N 82800 45600 82200 45600 4
N 82800 43600 82200 43600 4
N 82800 42400 82200 42400 4
N 82800 40800 82200 40800 4
N 82800 39400 82200 39400 4
N 82200 39400 82200 53900 4
N 85500 39400 85500 53900 4
C 85700 53900 1 0 1 3.3V-plus-1.sym
N 85500 52600 84900 52600 4
N 84900 51000 85500 51000 4
N 84900 49200 85500 49200 4
N 84900 47400 85500 47400 4
N 84900 45600 85500 45600 4
N 84900 43600 85500 43600 4
N 84900 42400 85500 42400 4
N 84900 40800 85500 40800 4
N 84900 39400 85500 39400 4
N 82800 53400 81100 53400 4
{
T 81200 53400 5 10 1 1 0 0 1
netname=DQ0
}
N 82800 53200 81100 53200 4
{
T 81200 53200 5 10 1 1 0 0 1
netname=DQ1
}
N 82800 53000 81100 53000 4
{
T 81200 53000 5 10 1 1 0 0 1
netname=DQ2
}
N 82800 52800 81100 52800 4
{
T 81200 52800 5 10 1 1 0 0 1
netname=DQ3
}
N 82800 52400 81100 52400 4
{
T 81200 52400 5 10 1 1 0 0 1
netname=DQ4
}
N 82800 52200 81100 52200 4
{
T 81200 52200 5 10 1 1 0 0 1
netname=DQ5
}
N 82800 52000 81100 52000 4
{
T 81200 52000 5 10 1 1 0 0 1
netname=DQ6
}
N 82800 51800 81100 51800 4
{
T 81200 51800 5 10 1 1 0 0 1
netname=DQ7
}
N 82800 50000 81100 50000 4
{
T 81200 50000 5 10 1 1 0 0 1
netname=DQ8
}
N 82800 49800 81100 49800 4
{
T 81200 49800 5 10 1 1 0 0 1
netname=DQ9
}
N 82800 49600 81100 49600 4
{
T 81200 49600 5 10 1 1 0 0 1
netname=DQ10
}
N 82800 49400 81100 49400 4
{
T 81200 49400 5 10 1 1 0 0 1
netname=DQ11
}
N 82800 51400 82400 51400 4
N 82800 51200 82400 51200 4
N 85300 51400 84900 51400 4
N 85300 51200 84900 51200 4
N 82800 42200 82400 42200 4
N 82800 42000 82400 42000 4
N 85300 42200 84900 42200 4
N 85300 42000 84900 42000 4
N 82800 49000 81100 49000 4
{
T 81200 49000 5 10 1 1 0 0 1
netname=DQ12
}
N 82800 48800 81100 48800 4
{
T 81200 48800 5 10 1 1 0 0 1
netname=DQ13
}
N 82800 48600 81100 48600 4
{
T 81200 48600 5 10 1 1 0 0 1
netname=DQ14
}
N 82800 48400 81100 48400 4
{
T 81200 48400 5 10 1 1 0 0 1
netname=DQ15
}
N 82800 45400 81100 45400 4
{
T 81200 45400 5 10 1 1 0 0 1
netname=DQ16
}
N 82800 45200 81100 45200 4
{
T 81200 45200 5 10 1 1 0 0 1
netname=DQ17
}
N 82800 45000 81100 45000 4
{
T 81200 45000 5 10 1 1 0 0 1
netname=DQ18
}
N 82800 44800 81100 44800 4
{
T 81200 44800 5 10 1 1 0 0 1
netname=DQ19
}
N 82800 44400 81100 44400 4
{
T 81200 44400 5 10 1 1 0 0 1
netname=DQ20
}
N 82800 44200 81100 44200 4
{
T 81200 44200 5 10 1 1 0 0 1
netname=DQ21
}
N 82800 44000 81100 44000 4
{
T 81200 44000 5 10 1 1 0 0 1
netname=DQ22
}
N 82800 43800 81100 43800 4
{
T 81200 43800 5 10 1 1 0 0 1
netname=DQ23
}
N 82800 41600 81100 41600 4
{
T 81200 41600 5 10 1 1 0 0 1
netname=DQ24
}
N 82800 41400 81100 41400 4
{
T 81200 41400 5 10 1 1 0 0 1
netname=DQ25
}
N 82800 41200 81100 41200 4
{
T 81200 41200 5 10 1 1 0 0 1
netname=DQ26
}
N 82800 41000 81100 41000 4
{
T 81200 41000 5 10 1 1 0 0 1
netname=DQ27
}
N 82800 40600 81100 40600 4
{
T 81200 40600 5 10 1 1 0 0 1
netname=DQ28
}
N 82800 40400 81100 40400 4
{
T 81200 40400 5 10 1 1 0 0 1
netname=DQ29
}
N 82800 40200 81100 40200 4
{
T 81200 40200 5 10 1 1 0 0 1
netname=DQ30
}
N 82800 40000 81100 40000 4
{
T 81200 40000 5 10 1 1 0 0 1
netname=DQ31
}
N 86600 53400 84900 53400 4
{
T 86000 53400 5 10 1 1 0 0 1
netname=DQ32
}
N 86600 53200 84900 53200 4
{
T 86000 53200 5 10 1 1 0 0 1
netname=DQ33
}
N 86600 53000 84900 53000 4
{
T 86000 53000 5 10 1 1 0 0 1
netname=DQ34
}
N 86600 52800 84900 52800 4
{
T 86000 52800 5 10 1 1 0 0 1
netname=DQ35
}
N 86600 52400 84900 52400 4
{
T 86000 52400 5 10 1 1 0 0 1
netname=DQ36
}
N 86600 52200 84900 52200 4
{
T 86000 52200 5 10 1 1 0 0 1
netname=DQ37
}
N 86600 52000 84900 52000 4
{
T 86000 52000 5 10 1 1 0 0 1
netname=DQ38
}
N 86600 51800 84900 51800 4
{
T 86000 51800 5 10 1 1 0 0 1
netname=DQ39
}
N 86600 50000 84900 50000 4
{
T 86000 50000 5 10 1 1 0 0 1
netname=DQ40
}
N 86600 49800 84900 49800 4
{
T 86000 49800 5 10 1 1 0 0 1
netname=DQ41
}
N 86600 49600 84900 49600 4
{
T 86000 49600 5 10 1 1 0 0 1
netname=DQ42
}
N 86600 49400 84900 49400 4
{
T 86000 49400 5 10 1 1 0 0 1
netname=DQ43
}
N 86600 49000 84900 49000 4
{
T 86000 49000 5 10 1 1 0 0 1
netname=DQ44
}
N 86600 48800 84900 48800 4
{
T 86000 48800 5 10 1 1 0 0 1
netname=DQ45
}
N 86600 48600 84900 48600 4
{
T 86000 48600 5 10 1 1 0 0 1
netname=DQ46
}
N 86600 48400 84900 48400 4
{
T 86000 48400 5 10 1 1 0 0 1
netname=DQ47
}
N 86600 45400 84900 45400 4
{
T 86000 45400 5 10 1 1 0 0 1
netname=DQ48
}
N 86600 45200 84900 45200 4
{
T 86000 45200 5 10 1 1 0 0 1
netname=DQ49
}
N 86600 45000 84900 45000 4
{
T 86000 45000 5 10 1 1 0 0 1
netname=DQ50
}
N 86600 44800 84900 44800 4
{
T 86000 44800 5 10 1 1 0 0 1
netname=DQ51
}
N 86600 44400 84900 44400 4
{
T 86000 44400 5 10 1 1 0 0 1
netname=DQ52
}
N 86600 44200 84900 44200 4
{
T 86000 44200 5 10 1 1 0 0 1
netname=DQ53
}
N 86600 44000 84900 44000 4
{
T 86000 44000 5 10 1 1 0 0 1
netname=DQ54
}
N 86600 43800 84900 43800 4
{
T 86000 43800 5 10 1 1 0 0 1
netname=DQ55
}
N 86600 41600 84900 41600 4
{
T 86000 41600 5 10 1 1 0 0 1
netname=DQ56
}
N 86600 41400 84900 41400 4
{
T 86000 41400 5 10 1 1 0 0 1
netname=DQ57
}
N 86600 41200 84900 41200 4
{
T 86000 41200 5 10 1 1 0 0 1
netname=DQ58
}
N 86600 41000 84900 41000 4
{
T 86000 41000 5 10 1 1 0 0 1
netname=DQ59
}
N 86600 40600 84900 40600 4
{
T 86000 40600 5 10 1 1 0 0 1
netname=DQ60
}
N 86600 40400 84900 40400 4
{
T 86000 40400 5 10 1 1 0 0 1
netname=DQ61
}
N 86600 40200 84900 40200 4
{
T 86000 40200 5 10 1 1 0 0 1
netname=DQ62
}
N 86600 40000 84900 40000 4
{
T 86000 40000 5 10 1 1 0 0 1
netname=DQ63
}
N 86600 39600 84900 39600 4
{
T 85700 39600 5 10 1 1 0 0 1
netname=SPD_SCL
}
N 82800 39600 81100 39600 4
{
T 81200 39600 5 10 1 1 0 0 1
netname=SPD_SDA
}
N 82800 43400 81100 43400 4
{
T 81200 43400 5 10 1 1 0 0 1
netname=A6
}
N 82800 43200 81100 43200 4
{
T 81200 43200 5 10 1 1 0 0 1
netname=A8
}
N 82800 42800 81100 42800 4
{
T 81200 42800 5 10 1 1 0 0 1
netname=A9
}
N 82800 42600 81100 42600 4
{
T 81200 42600 5 10 1 1 0 0 1
netname=A10
}
N 82800 50800 81100 50800 4
{
T 81200 50800 5 10 1 1 0 0 1
netname=A0
}
N 82800 50600 81100 50600 4
{
T 81200 50600 5 10 1 1 0 0 1
netname=A1
}
N 82800 50400 81100 50400 4
{
T 81200 50400 5 10 1 1 0 0 1
netname=A2
}
N 86600 50800 84900 50800 4
{
T 86200 50800 5 10 1 1 0 0 1
netname=A3
}
N 86600 50600 84900 50600 4
{
T 86200 50600 5 10 1 1 0 0 1
netname=A4
}
N 86600 50400 84900 50400 4
{
T 86200 50400 5 10 1 1 0 0 1
netname=A5
}
N 86600 46800 84900 46800 4
{
T 86200 46800 5 10 1 1 0 0 1
netname=A12
}
N 86600 43400 84900 43400 4
{
T 86200 43400 5 10 1 1 0 0 1
netname=A7
}
N 86600 42600 84900 42600 4
{
T 86200 42600 5 10 1 1 0 0 1
netname=A11
}
N 86600 43200 84900 43200 4
{
T 86100 43200 5 10 1 1 0 0 1
netname=BA0
}
N 86600 42800 84900 42800 4
{
T 86100 42800 5 10 1 1 0 0 1
netname=BA1
}
N 86600 47200 84900 47200 4
{
T 86000 47200 5 10 1 1 0 0 1
netname=nCAS
}
N 82800 47200 81100 47200 4
{
T 81200 47200 5 10 1 1 0 0 1
netname=nRAS
}
N 82800 47600 81100 47600 4
{
T 81200 47600 5 10 1 1 0 0 1
netname=CK0
}
N 86600 47600 84900 47600 4
{
T 86000 47600 5 10 1 1 0 0 1
netname=CKE0
}
N 82800 46800 82400 46800 4
N 82800 47000 81100 47000 4
{
T 81200 47000 5 10 1 1 0 0 1
netname=nWE
}
T 81900 37900 9 10 1 0 0 0 3
Only single-rank modules <= 128MB supported
Modules must be 133MHz or faster
Module has internal bypass caps

v 20050313 1 1
P 100 14500 400 14500 1 0 0
{
T 300 14550 5 8 1 1 0 6 1
pinnumber=1
T 300 14450 5 8 0 1 0 8 1
pinseq=1
T 450 14500 9 8 1 1 0 0 1
pinlabel=VSS
T 450 14500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 14500 1900 14500 1 0 0
{
T 2000 14550 5 8 1 1 0 0 1
pinnumber=2
T 2000 14450 5 8 0 1 0 2 1
pinseq=2
T 1850 14500 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 14500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 14300 400 14300 1 0 0
{
T 300 14350 5 8 1 1 0 6 1
pinnumber=3
T 300 14250 5 8 0 1 0 8 1
pinseq=3
T 450 14300 9 8 1 1 0 0 1
pinlabel=DQ0
T 450 14300 5 8 0 1 0 2 1
pintype=io
}
P 2200 14300 1900 14300 1 0 0
{
T 2000 14350 5 8 1 1 0 0 1
pinnumber=4
T 2000 14250 5 8 0 1 0 2 1
pinseq=4
T 1850 14300 9 8 1 1 0 6 1
pinlabel=DQ32
T 1850 14300 5 8 0 1 0 8 1
pintype=io
}
P 100 14100 400 14100 1 0 0
{
T 300 14150 5 8 1 1 0 6 1
pinnumber=5
T 300 14050 5 8 0 1 0 8 1
pinseq=5
T 450 14100 9 8 1 1 0 0 1
pinlabel=DQ1
T 450 14100 5 8 0 1 0 2 1
pintype=io
}
P 2200 14100 1900 14100 1 0 0
{
T 2000 14150 5 8 1 1 0 0 1
pinnumber=6
T 2000 14050 5 8 0 1 0 2 1
pinseq=6
T 1850 14100 9 8 1 1 0 6 1
pinlabel=DQ33
T 1850 14100 5 8 0 1 0 8 1
pintype=io
}
P 100 13900 400 13900 1 0 0
{
T 300 13950 5 8 1 1 0 6 1
pinnumber=7
T 300 13850 5 8 0 1 0 8 1
pinseq=7
T 450 13900 9 8 1 1 0 0 1
pinlabel=DQ2
T 450 13900 5 8 0 1 0 2 1
pintype=io
}
P 2200 13900 1900 13900 1 0 0
{
T 2000 13950 5 8 1 1 0 0 1
pinnumber=8
T 2000 13850 5 8 0 1 0 2 1
pinseq=8
T 1850 13900 9 8 1 1 0 6 1
pinlabel=DQ34
T 1850 13900 5 8 0 1 0 8 1
pintype=io
}
P 100 13700 400 13700 1 0 0
{
T 300 13750 5 8 1 1 0 6 1
pinnumber=9
T 300 13650 5 8 0 1 0 8 1
pinseq=9
T 450 13700 9 8 1 1 0 0 1
pinlabel=DQ3
T 450 13700 5 8 0 1 0 2 1
pintype=io
}
P 2200 13700 1900 13700 1 0 0
{
T 2000 13750 5 8 1 1 0 0 1
pinnumber=10
T 2000 13650 5 8 0 1 0 2 1
pinseq=10
T 1850 13700 9 8 1 1 0 6 1
pinlabel=DQ35
T 1850 13700 5 8 0 1 0 8 1
pintype=io
}
P 100 13500 400 13500 1 0 0
{
T 300 13550 5 8 1 1 0 6 1
pinnumber=11
T 300 13450 5 8 0 1 0 8 1
pinseq=11
T 450 13500 9 8 1 1 0 0 1
pinlabel=VDD
T 450 13500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 13500 1900 13500 1 0 0
{
T 2000 13550 5 8 1 1 0 0 1
pinnumber=12
T 2000 13450 5 8 0 1 0 2 1
pinseq=12
T 1850 13500 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 13500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 13300 400 13300 1 0 0
{
T 300 13350 5 8 1 1 0 6 1
pinnumber=13
T 300 13250 5 8 0 1 0 8 1
pinseq=13
T 450 13300 9 8 1 1 0 0 1
pinlabel=DQ4
T 450 13300 5 8 0 1 0 2 1
pintype=io
}
P 2200 13300 1900 13300 1 0 0
{
T 2000 13350 5 8 1 1 0 0 1
pinnumber=14
T 2000 13250 5 8 0 1 0 2 1
pinseq=14
T 1850 13300 9 8 1 1 0 6 1
pinlabel=DQ36
T 1850 13300 5 8 0 1 0 8 1
pintype=io
}
P 100 13100 400 13100 1 0 0
{
T 300 13150 5 8 1 1 0 6 1
pinnumber=15
T 300 13050 5 8 0 1 0 8 1
pinseq=15
T 450 13100 9 8 1 1 0 0 1
pinlabel=DQ5
T 450 13100 5 8 0 1 0 2 1
pintype=io
}
P 2200 13100 1900 13100 1 0 0
{
T 2000 13150 5 8 1 1 0 0 1
pinnumber=16
T 2000 13050 5 8 0 1 0 2 1
pinseq=16
T 1850 13100 9 8 1 1 0 6 1
pinlabel=DQ37
T 1850 13100 5 8 0 1 0 8 1
pintype=io
}
P 100 12900 400 12900 1 0 0
{
T 300 12950 5 8 1 1 0 6 1
pinnumber=17
T 300 12850 5 8 0 1 0 8 1
pinseq=17
T 450 12900 9 8 1 1 0 0 1
pinlabel=DQ6
T 450 12900 5 8 0 1 0 2 1
pintype=io
}
P 2200 12900 1900 12900 1 0 0
{
T 2000 12950 5 8 1 1 0 0 1
pinnumber=18
T 2000 12850 5 8 0 1 0 2 1
pinseq=18
T 1850 12900 9 8 1 1 0 6 1
pinlabel=DQ38
T 1850 12900 5 8 0 1 0 8 1
pintype=io
}
P 100 12700 400 12700 1 0 0
{
T 300 12750 5 8 1 1 0 6 1
pinnumber=19
T 300 12650 5 8 0 1 0 8 1
pinseq=19
T 450 12700 9 8 1 1 0 0 1
pinlabel=DQ7
T 450 12700 5 8 0 1 0 2 1
pintype=io
}
P 2200 12700 1900 12700 1 0 0
{
T 2000 12750 5 8 1 1 0 0 1
pinnumber=20
T 2000 12650 5 8 0 1 0 2 1
pinseq=20
T 1850 12700 9 8 1 1 0 6 1
pinlabel=DQ39
T 1850 12700 5 8 0 1 0 8 1
pintype=io
}
P 100 12500 400 12500 1 0 0
{
T 300 12550 5 8 1 1 0 6 1
pinnumber=21
T 300 12450 5 8 0 1 0 8 1
pinseq=21
T 450 12500 9 8 1 1 0 0 1
pinlabel=VSS
T 450 12500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 12500 1900 12500 1 0 0
{
T 2000 12550 5 8 1 1 0 0 1
pinnumber=22
T 2000 12450 5 8 0 1 0 2 1
pinseq=22
T 1850 12500 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 12500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 12300 400 12300 1 0 0
{
T 300 12350 5 8 1 1 0 6 1
pinnumber=23
T 300 12250 5 8 0 1 0 8 1
pinseq=23
T 450 12300 9 8 1 1 0 0 1
pinlabel=DQMB0
T 450 12300 5 8 0 1 0 2 1
pintype=in
}
P 2200 12300 1900 12300 1 0 0
{
T 2000 12350 5 8 1 1 0 0 1
pinnumber=24
T 2000 12250 5 8 0 1 0 2 1
pinseq=24
T 1850 12300 9 8 1 1 0 6 1
pinlabel=DQMB4
T 1850 12300 5 8 0 1 0 8 1
pintype=in
}
P 100 12100 400 12100 1 0 0
{
T 300 12150 5 8 1 1 0 6 1
pinnumber=25
T 300 12050 5 8 0 1 0 8 1
pinseq=25
T 450 12100 9 8 1 1 0 0 1
pinlabel=DQMB1
T 450 12100 5 8 0 1 0 2 1
pintype=in
}
P 2200 12100 1900 12100 1 0 0
{
T 2000 12150 5 8 1 1 0 0 1
pinnumber=26
T 2000 12050 5 8 0 1 0 2 1
pinseq=26
T 1850 12100 9 8 1 1 0 6 1
pinlabel=DQMB5
T 1850 12100 5 8 0 1 0 8 1
pintype=in
}
P 100 11900 400 11900 1 0 0
{
T 300 11950 5 8 1 1 0 6 1
pinnumber=27
T 300 11850 5 8 0 1 0 8 1
pinseq=27
T 450 11900 9 8 1 1 0 0 1
pinlabel=VDD
T 450 11900 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 11900 1900 11900 1 0 0
{
T 2000 11950 5 8 1 1 0 0 1
pinnumber=28
T 2000 11850 5 8 0 1 0 2 1
pinseq=28
T 1850 11900 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 11900 5 8 0 1 0 8 1
pintype=pwr
}
P 100 11700 400 11700 1 0 0
{
T 300 11750 5 8 1 1 0 6 1
pinnumber=29
T 300 11650 5 8 0 1 0 8 1
pinseq=29
T 450 11700 9 8 1 1 0 0 1
pinlabel=A0
T 450 11700 5 8 0 1 0 2 1
pintype=in
}
P 2200 11700 1900 11700 1 0 0
{
T 2000 11750 5 8 1 1 0 0 1
pinnumber=30
T 2000 11650 5 8 0 1 0 2 1
pinseq=30
T 1850 11700 9 8 1 1 0 6 1
pinlabel=A3
T 1850 11700 5 8 0 1 0 8 1
pintype=in
}
P 100 11500 400 11500 1 0 0
{
T 300 11550 5 8 1 1 0 6 1
pinnumber=31
T 300 11450 5 8 0 1 0 8 1
pinseq=31
T 450 11500 9 8 1 1 0 0 1
pinlabel=A1
T 450 11500 5 8 0 1 0 2 1
pintype=in
}
P 2200 11500 1900 11500 1 0 0
{
T 2000 11550 5 8 1 1 0 0 1
pinnumber=32
T 2000 11450 5 8 0 1 0 2 1
pinseq=32
T 1850 11500 9 8 1 1 0 6 1
pinlabel=A4
T 1850 11500 5 8 0 1 0 8 1
pintype=in
}
P 100 11300 400 11300 1 0 0
{
T 300 11350 5 8 1 1 0 6 1
pinnumber=33
T 300 11250 5 8 0 1 0 8 1
pinseq=33
T 450 11300 9 8 1 1 0 0 1
pinlabel=A2
T 450 11300 5 8 0 1 0 2 1
pintype=in
}
P 2200 11300 1900 11300 1 0 0
{
T 2000 11350 5 8 1 1 0 0 1
pinnumber=34
T 2000 11250 5 8 0 1 0 2 1
pinseq=34
T 1850 11300 9 8 1 1 0 6 1
pinlabel=A5
T 1850 11300 5 8 0 1 0 8 1
pintype=in
}
P 100 11100 400 11100 1 0 0
{
T 300 11150 5 8 1 1 0 6 1
pinnumber=35
T 300 11050 5 8 0 1 0 8 1
pinseq=35
T 450 11100 9 8 1 1 0 0 1
pinlabel=VSS
T 450 11100 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 11100 1900 11100 1 0 0
{
T 2000 11150 5 8 1 1 0 0 1
pinnumber=36
T 2000 11050 5 8 0 1 0 2 1
pinseq=36
T 1850 11100 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 11100 5 8 0 1 0 8 1
pintype=pwr
}
P 100 10900 400 10900 1 0 0
{
T 300 10950 5 8 1 1 0 6 1
pinnumber=37
T 300 10850 5 8 0 1 0 8 1
pinseq=37
T 450 10900 9 8 1 1 0 0 1
pinlabel=DQ8
T 450 10900 5 8 0 1 0 2 1
pintype=io
}
P 2200 10900 1900 10900 1 0 0
{
T 2000 10950 5 8 1 1 0 0 1
pinnumber=38
T 2000 10850 5 8 0 1 0 2 1
pinseq=38
T 1850 10900 9 8 1 1 0 6 1
pinlabel=DQ40
T 1850 10900 5 8 0 1 0 8 1
pintype=io
}
P 100 10700 400 10700 1 0 0
{
T 300 10750 5 8 1 1 0 6 1
pinnumber=39
T 300 10650 5 8 0 1 0 8 1
pinseq=39
T 450 10700 9 8 1 1 0 0 1
pinlabel=DQ9
T 450 10700 5 8 0 1 0 2 1
pintype=io
}
P 2200 10700 1900 10700 1 0 0
{
T 2000 10750 5 8 1 1 0 0 1
pinnumber=40
T 2000 10650 5 8 0 1 0 2 1
pinseq=40
T 1850 10700 9 8 1 1 0 6 1
pinlabel=DQ41
T 1850 10700 5 8 0 1 0 8 1
pintype=io
}
P 100 10500 400 10500 1 0 0
{
T 300 10550 5 8 1 1 0 6 1
pinnumber=41
T 300 10450 5 8 0 1 0 8 1
pinseq=41
T 450 10500 9 8 1 1 0 0 1
pinlabel=DQ10
T 450 10500 5 8 0 1 0 2 1
pintype=io
}
P 2200 10500 1900 10500 1 0 0
{
T 2000 10550 5 8 1 1 0 0 1
pinnumber=42
T 2000 10450 5 8 0 1 0 2 1
pinseq=42
T 1850 10500 9 8 1 1 0 6 1
pinlabel=DQ42
T 1850 10500 5 8 0 1 0 8 1
pintype=io
}
P 100 10300 400 10300 1 0 0
{
T 300 10350 5 8 1 1 0 6 1
pinnumber=43
T 300 10250 5 8 0 1 0 8 1
pinseq=43
T 450 10300 9 8 1 1 0 0 1
pinlabel=DQ11
T 450 10300 5 8 0 1 0 2 1
pintype=io
}
P 2200 10300 1900 10300 1 0 0
{
T 2000 10350 5 8 1 1 0 0 1
pinnumber=44
T 2000 10250 5 8 0 1 0 2 1
pinseq=44
T 1850 10300 9 8 1 1 0 6 1
pinlabel=DQ43
T 1850 10300 5 8 0 1 0 8 1
pintype=io
}
P 100 10100 400 10100 1 0 0
{
T 300 10150 5 8 1 1 0 6 1
pinnumber=45
T 300 10050 5 8 0 1 0 8 1
pinseq=45
T 450 10100 9 8 1 1 0 0 1
pinlabel=VDD
T 450 10100 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 10100 1900 10100 1 0 0
{
T 2000 10150 5 8 1 1 0 0 1
pinnumber=46
T 2000 10050 5 8 0 1 0 2 1
pinseq=46
T 1850 10100 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 10100 5 8 0 1 0 8 1
pintype=pwr
}
P 100 9900 400 9900 1 0 0
{
T 300 9950 5 8 1 1 0 6 1
pinnumber=47
T 300 9850 5 8 0 1 0 8 1
pinseq=47
T 450 9900 9 8 1 1 0 0 1
pinlabel=DQ12
T 450 9900 5 8 0 1 0 2 1
pintype=io
}
P 2200 9900 1900 9900 1 0 0
{
T 2000 9950 5 8 1 1 0 0 1
pinnumber=48
T 2000 9850 5 8 0 1 0 2 1
pinseq=48
T 1850 9900 9 8 1 1 0 6 1
pinlabel=DQ44
T 1850 9900 5 8 0 1 0 8 1
pintype=io
}
P 100 9700 400 9700 1 0 0
{
T 300 9750 5 8 1 1 0 6 1
pinnumber=49
T 300 9650 5 8 0 1 0 8 1
pinseq=49
T 450 9700 9 8 1 1 0 0 1
pinlabel=DQ13
T 450 9700 5 8 0 1 0 2 1
pintype=io
}
P 2200 9700 1900 9700 1 0 0
{
T 2000 9750 5 8 1 1 0 0 1
pinnumber=50
T 2000 9650 5 8 0 1 0 2 1
pinseq=50
T 1850 9700 9 8 1 1 0 6 1
pinlabel=DQ45
T 1850 9700 5 8 0 1 0 8 1
pintype=io
}
P 100 9500 400 9500 1 0 0
{
T 300 9550 5 8 1 1 0 6 1
pinnumber=51
T 300 9450 5 8 0 1 0 8 1
pinseq=51
T 450 9500 9 8 1 1 0 0 1
pinlabel=DQ14
T 450 9500 5 8 0 1 0 2 1
pintype=io
}
P 2200 9500 1900 9500 1 0 0
{
T 2000 9550 5 8 1 1 0 0 1
pinnumber=52
T 2000 9450 5 8 0 1 0 2 1
pinseq=52
T 1850 9500 9 8 1 1 0 6 1
pinlabel=DQ46
T 1850 9500 5 8 0 1 0 8 1
pintype=io
}
P 100 9300 400 9300 1 0 0
{
T 300 9350 5 8 1 1 0 6 1
pinnumber=53
T 300 9250 5 8 0 1 0 8 1
pinseq=53
T 450 9300 9 8 1 1 0 0 1
pinlabel=DQ15
T 450 9300 5 8 0 1 0 2 1
pintype=io
}
P 2200 9300 1900 9300 1 0 0
{
T 2000 9350 5 8 1 1 0 0 1
pinnumber=54
T 2000 9250 5 8 0 1 0 2 1
pinseq=54
T 1850 9300 9 8 1 1 0 6 1
pinlabel=DQ47
T 1850 9300 5 8 0 1 0 8 1
pintype=io
}
P 100 9100 400 9100 1 0 0
{
T 300 9150 5 8 1 1 0 6 1
pinnumber=55
T 300 9050 5 8 0 1 0 8 1
pinseq=55
T 450 9100 9 8 1 1 0 0 1
pinlabel=VSS
T 450 9100 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 9100 1900 9100 1 0 0
{
T 2000 9150 5 8 1 1 0 0 1
pinnumber=56
T 2000 9050 5 8 0 1 0 2 1
pinseq=56
T 1850 9100 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 9100 5 8 0 1 0 8 1
pintype=pwr
}
P 100 8900 400 8900 1 0 0
{
T 300 8950 5 8 1 1 0 6 1
pinnumber=57
T 300 8850 5 8 0 1 0 8 1
pinseq=57
T 450 8900 9 8 1 1 0 0 1
pinlabel=DNU
T 450 8900 5 8 0 1 0 2 1
pintype=io
}
P 2200 8900 1900 8900 1 0 0
{
T 2000 8950 5 8 1 1 0 0 1
pinnumber=58
T 2000 8850 5 8 0 1 0 2 1
pinseq=58
T 1850 8900 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 8900 5 8 0 1 0 8 1
pintype=io
}
P 100 8700 400 8700 1 0 0
{
T 300 8750 5 8 1 1 0 6 1
pinnumber=59
T 300 8650 5 8 0 1 0 8 1
pinseq=59
T 450 8700 9 8 1 1 0 0 1
pinlabel=DNU
T 450 8700 5 8 0 1 0 2 1
pintype=io
}
P 2200 8700 1900 8700 1 0 0
{
T 2000 8750 5 8 1 1 0 0 1
pinnumber=60
T 2000 8650 5 8 0 1 0 2 1
pinseq=60
T 1850 8700 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 8700 5 8 0 1 0 8 1
pintype=io
}
P 100 8500 400 8500 1 0 0
{
T 300 8550 5 8 1 1 0 6 1
pinnumber=61
T 300 8450 5 8 0 1 0 8 1
pinseq=61
T 450 8500 9 8 1 1 0 0 1
pinlabel=CK0
T 450 8500 5 8 0 1 0 2 1
pintype=in
}
P 2200 8500 1900 8500 1 0 0
{
T 2000 8550 5 8 1 1 0 0 1
pinnumber=62
T 2000 8450 5 8 0 1 0 2 1
pinseq=62
T 1850 8500 9 8 1 1 0 6 1
pinlabel=CKE0
T 1850 8500 5 8 0 1 0 8 1
pintype=in
}
P 100 8300 400 8300 1 0 0
{
T 300 8350 5 8 1 1 0 6 1
pinnumber=63
T 300 8250 5 8 0 1 0 8 1
pinseq=63
T 450 8300 9 8 1 1 0 0 1
pinlabel=VDD
T 450 8300 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 8300 1900 8300 1 0 0
{
T 2000 8350 5 8 1 1 0 0 1
pinnumber=64
T 2000 8250 5 8 0 1 0 2 1
pinseq=64
T 1850 8300 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 8300 5 8 0 1 0 8 1
pintype=pwr
}
P 100 8100 400 8100 1 0 0
{
T 300 8150 5 8 1 1 0 6 1
pinnumber=65
T 300 8050 5 8 0 1 0 8 1
pinseq=65
T 450 8100 9 8 1 1 0 0 1
pinlabel=\_RAS\_
T 450 8100 5 8 0 1 0 2 1
pintype=in
}
P 2200 8100 1900 8100 1 0 0
{
T 2000 8150 5 8 1 1 0 0 1
pinnumber=66
T 2000 8050 5 8 0 1 0 2 1
pinseq=66
T 1850 8100 9 8 1 1 0 6 1
pinlabel=\_CAS\_
T 1850 8100 5 8 0 1 0 8 1
pintype=in
}
P 100 7900 400 7900 1 0 0
{
T 300 7950 5 8 1 1 0 6 1
pinnumber=67
T 300 7850 5 8 0 1 0 8 1
pinseq=67
T 450 7900 9 8 1 1 0 0 1
pinlabel=\_WE\_
T 450 7900 5 8 0 1 0 2 1
pintype=in
}
P 2200 7900 1900 7900 1 0 0
{
T 2000 7950 5 8 1 1 0 0 1
pinnumber=68
T 2000 7850 5 8 0 1 0 2 1
pinseq=68
T 1850 7900 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 7900 5 8 0 1 0 8 1
pintype=io
}
P 100 7700 400 7700 1 0 0
{
T 300 7750 5 8 1 1 0 6 1
pinnumber=69
T 300 7650 5 8 0 1 0 8 1
pinseq=69
T 450 7700 9 8 1 1 0 0 1
pinlabel=\_S0\_
T 450 7700 5 8 0 1 0 2 1
pintype=in
}
P 2200 7700 1900 7700 1 0 0
{
T 2000 7750 5 8 1 1 0 0 1
pinnumber=70
T 2000 7650 5 8 0 1 0 2 1
pinseq=70
T 1850 7700 9 8 1 1 0 6 1
pinlabel=A12
T 1850 7700 5 8 0 1 0 8 1
pintype=in
}
P 100 7500 400 7500 1 0 0
{
T 300 7550 5 8 1 1 0 6 1
pinnumber=71
T 300 7450 5 8 0 1 0 8 1
pinseq=71
T 450 7500 9 8 1 1 0 0 1
pinlabel=DNU
T 450 7500 5 8 0 1 0 2 1
pintype=io
}
P 2200 7500 1900 7500 1 0 0
{
T 2000 7550 5 8 1 1 0 0 1
pinnumber=72
T 2000 7450 5 8 0 1 0 2 1
pinseq=72
T 1850 7500 9 8 1 1 0 6 1
pinlabel=NC
T 1850 7500 5 8 0 1 0 8 1
pintype=io
}
P 100 7300 400 7300 1 0 0
{
T 300 7350 5 8 1 1 0 6 1
pinnumber=73
T 300 7250 5 8 0 1 0 8 1
pinseq=73
T 450 7300 9 8 1 1 0 0 1
pinlabel=NC
T 450 7300 5 8 0 1 0 2 1
pintype=io
}
P 2200 7300 1900 7300 1 0 0
{
T 2000 7350 5 8 1 1 0 0 1
pinnumber=74
T 2000 7250 5 8 0 1 0 2 1
pinseq=74
T 1850 7300 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 7300 5 8 0 1 0 8 1
pintype=io
}
P 100 7100 400 7100 1 0 0
{
T 300 7150 5 8 1 1 0 6 1
pinnumber=75
T 300 7050 5 8 0 1 0 8 1
pinseq=75
T 450 7100 9 8 1 1 0 0 1
pinlabel=VSS
T 450 7100 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 7100 1900 7100 1 0 0
{
T 2000 7150 5 8 1 1 0 0 1
pinnumber=76
T 2000 7050 5 8 0 1 0 2 1
pinseq=76
T 1850 7100 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 7100 5 8 0 1 0 8 1
pintype=pwr
}
P 100 6900 400 6900 1 0 0
{
T 300 6950 5 8 1 1 0 6 1
pinnumber=77
T 300 6850 5 8 0 1 0 8 1
pinseq=77
T 450 6900 9 8 1 1 0 0 1
pinlabel=DNU
T 450 6900 5 8 0 1 0 2 1
pintype=io
}
P 2200 6900 1900 6900 1 0 0
{
T 2000 6950 5 8 1 1 0 0 1
pinnumber=78
T 2000 6850 5 8 0 1 0 2 1
pinseq=78
T 1850 6900 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 6900 5 8 0 1 0 8 1
pintype=io
}
P 100 6700 400 6700 1 0 0
{
T 300 6750 5 8 1 1 0 6 1
pinnumber=79
T 300 6650 5 8 0 1 0 8 1
pinseq=79
T 450 6700 9 8 1 1 0 0 1
pinlabel=DNU
T 450 6700 5 8 0 1 0 2 1
pintype=io
}
P 2200 6700 1900 6700 1 0 0
{
T 2000 6750 5 8 1 1 0 0 1
pinnumber=80
T 2000 6650 5 8 0 1 0 2 1
pinseq=80
T 1850 6700 9 8 1 1 0 6 1
pinlabel=DNU
T 1850 6700 5 8 0 1 0 8 1
pintype=io
}
P 100 6500 400 6500 1 0 0
{
T 300 6550 5 8 1 1 0 6 1
pinnumber=81
T 300 6450 5 8 0 1 0 8 1
pinseq=81
T 450 6500 9 8 1 1 0 0 1
pinlabel=VDD
T 450 6500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 6500 1900 6500 1 0 0
{
T 2000 6550 5 8 1 1 0 0 1
pinnumber=82
T 2000 6450 5 8 0 1 0 2 1
pinseq=82
T 1850 6500 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 6500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 6300 400 6300 1 0 0
{
T 300 6350 5 8 1 1 0 6 1
pinnumber=83
T 300 6250 5 8 0 1 0 8 1
pinseq=83
T 450 6300 9 8 1 1 0 0 1
pinlabel=DQ16
T 450 6300 5 8 0 1 0 2 1
pintype=io
}
P 2200 6300 1900 6300 1 0 0
{
T 2000 6350 5 8 1 1 0 0 1
pinnumber=84
T 2000 6250 5 8 0 1 0 2 1
pinseq=84
T 1850 6300 9 8 1 1 0 6 1
pinlabel=DQ48
T 1850 6300 5 8 0 1 0 8 1
pintype=io
}
P 100 6100 400 6100 1 0 0
{
T 300 6150 5 8 1 1 0 6 1
pinnumber=85
T 300 6050 5 8 0 1 0 8 1
pinseq=85
T 450 6100 9 8 1 1 0 0 1
pinlabel=DQ17
T 450 6100 5 8 0 1 0 2 1
pintype=io
}
P 2200 6100 1900 6100 1 0 0
{
T 2000 6150 5 8 1 1 0 0 1
pinnumber=86
T 2000 6050 5 8 0 1 0 2 1
pinseq=86
T 1850 6100 9 8 1 1 0 6 1
pinlabel=DQ49
T 1850 6100 5 8 0 1 0 8 1
pintype=io
}
P 100 5900 400 5900 1 0 0
{
T 300 5950 5 8 1 1 0 6 1
pinnumber=87
T 300 5850 5 8 0 1 0 8 1
pinseq=87
T 450 5900 9 8 1 1 0 0 1
pinlabel=DQ18
T 450 5900 5 8 0 1 0 2 1
pintype=io
}
P 2200 5900 1900 5900 1 0 0
{
T 2000 5950 5 8 1 1 0 0 1
pinnumber=88
T 2000 5850 5 8 0 1 0 2 1
pinseq=88
T 1850 5900 9 8 1 1 0 6 1
pinlabel=DQ50
T 1850 5900 5 8 0 1 0 8 1
pintype=io
}
P 100 5700 400 5700 1 0 0
{
T 300 5750 5 8 1 1 0 6 1
pinnumber=89
T 300 5650 5 8 0 1 0 8 1
pinseq=89
T 450 5700 9 8 1 1 0 0 1
pinlabel=DQ19
T 450 5700 5 8 0 1 0 2 1
pintype=io
}
P 2200 5700 1900 5700 1 0 0
{
T 2000 5750 5 8 1 1 0 0 1
pinnumber=90
T 2000 5650 5 8 0 1 0 2 1
pinseq=90
T 1850 5700 9 8 1 1 0 6 1
pinlabel=DQ51
T 1850 5700 5 8 0 1 0 8 1
pintype=io
}
P 100 5500 400 5500 1 0 0
{
T 300 5550 5 8 1 1 0 6 1
pinnumber=91
T 300 5450 5 8 0 1 0 8 1
pinseq=91
T 450 5500 9 8 1 1 0 0 1
pinlabel=VSS
T 450 5500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 5500 1900 5500 1 0 0
{
T 2000 5550 5 8 1 1 0 0 1
pinnumber=92
T 2000 5450 5 8 0 1 0 2 1
pinseq=92
T 1850 5500 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 5500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 5300 400 5300 1 0 0
{
T 300 5350 5 8 1 1 0 6 1
pinnumber=93
T 300 5250 5 8 0 1 0 8 1
pinseq=93
T 450 5300 9 8 1 1 0 0 1
pinlabel=DQ20
T 450 5300 5 8 0 1 0 2 1
pintype=io
}
P 2200 5300 1900 5300 1 0 0
{
T 2000 5350 5 8 1 1 0 0 1
pinnumber=94
T 2000 5250 5 8 0 1 0 2 1
pinseq=94
T 1850 5300 9 8 1 1 0 6 1
pinlabel=DQ52
T 1850 5300 5 8 0 1 0 8 1
pintype=io
}
P 100 5100 400 5100 1 0 0
{
T 300 5150 5 8 1 1 0 6 1
pinnumber=95
T 300 5050 5 8 0 1 0 8 1
pinseq=95
T 450 5100 9 8 1 1 0 0 1
pinlabel=DQ21
T 450 5100 5 8 0 1 0 2 1
pintype=io
}
P 2200 5100 1900 5100 1 0 0
{
T 2000 5150 5 8 1 1 0 0 1
pinnumber=96
T 2000 5050 5 8 0 1 0 2 1
pinseq=96
T 1850 5100 9 8 1 1 0 6 1
pinlabel=DQ53
T 1850 5100 5 8 0 1 0 8 1
pintype=io
}
P 100 4900 400 4900 1 0 0
{
T 300 4950 5 8 1 1 0 6 1
pinnumber=97
T 300 4850 5 8 0 1 0 8 1
pinseq=97
T 450 4900 9 8 1 1 0 0 1
pinlabel=DQ22
T 450 4900 5 8 0 1 0 2 1
pintype=io
}
P 2200 4900 1900 4900 1 0 0
{
T 2000 4950 5 8 1 1 0 0 1
pinnumber=98
T 2000 4850 5 8 0 1 0 2 1
pinseq=98
T 1850 4900 9 8 1 1 0 6 1
pinlabel=DQ54
T 1850 4900 5 8 0 1 0 8 1
pintype=io
}
P 100 4700 400 4700 1 0 0
{
T 300 4750 5 8 1 1 0 6 1
pinnumber=99
T 300 4650 5 8 0 1 0 8 1
pinseq=99
T 450 4700 9 8 1 1 0 0 1
pinlabel=DQ23
T 450 4700 5 8 0 1 0 2 1
pintype=io
}
P 2200 4700 1900 4700 1 0 0
{
T 2000 4750 5 8 1 1 0 0 1
pinnumber=100
T 2000 4650 5 8 0 1 0 2 1
pinseq=100
T 1850 4700 9 8 1 1 0 6 1
pinlabel=DQ55
T 1850 4700 5 8 0 1 0 8 1
pintype=io
}
P 100 4500 400 4500 1 0 0
{
T 300 4550 5 8 1 1 0 6 1
pinnumber=101
T 300 4450 5 8 0 1 0 8 1
pinseq=101
T 450 4500 9 8 1 1 0 0 1
pinlabel=VDD
T 450 4500 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 4500 1900 4500 1 0 0
{
T 2000 4550 5 8 1 1 0 0 1
pinnumber=102
T 2000 4450 5 8 0 1 0 2 1
pinseq=102
T 1850 4500 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 4500 5 8 0 1 0 8 1
pintype=pwr
}
P 100 4300 400 4300 1 0 0
{
T 300 4350 5 8 1 1 0 6 1
pinnumber=103
T 300 4250 5 8 0 1 0 8 1
pinseq=103
T 450 4300 9 8 1 1 0 0 1
pinlabel=A6
T 450 4300 5 8 0 1 0 2 1
pintype=in
}
P 2200 4300 1900 4300 1 0 0
{
T 2000 4350 5 8 1 1 0 0 1
pinnumber=104
T 2000 4250 5 8 0 1 0 2 1
pinseq=104
T 1850 4300 9 8 1 1 0 6 1
pinlabel=A7
T 1850 4300 5 8 0 1 0 8 1
pintype=in
}
P 100 4100 400 4100 1 0 0
{
T 300 4150 5 8 1 1 0 6 1
pinnumber=105
T 300 4050 5 8 0 1 0 8 1
pinseq=105
T 450 4100 9 8 1 1 0 0 1
pinlabel=A8
T 450 4100 5 8 0 1 0 2 1
pintype=in
}
P 2200 4100 1900 4100 1 0 0
{
T 2000 4150 5 8 1 1 0 0 1
pinnumber=106
T 2000 4050 5 8 0 1 0 2 1
pinseq=106
T 1850 4100 9 8 1 1 0 6 1
pinlabel=BA0
T 1850 4100 5 8 0 1 0 8 1
pintype=in
}
P 100 3900 400 3900 1 0 0
{
T 300 3950 5 8 1 1 0 6 1
pinnumber=107
T 300 3850 5 8 0 1 0 8 1
pinseq=107
T 450 3900 9 8 1 1 0 0 1
pinlabel=VSS
T 450 3900 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 3900 1900 3900 1 0 0
{
T 2000 3950 5 8 1 1 0 0 1
pinnumber=108
T 2000 3850 5 8 0 1 0 2 1
pinseq=108
T 1850 3900 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 3900 5 8 0 1 0 8 1
pintype=pwr
}
P 100 3700 400 3700 1 0 0
{
T 300 3750 5 8 1 1 0 6 1
pinnumber=109
T 300 3650 5 8 0 1 0 8 1
pinseq=109
T 450 3700 9 8 1 1 0 0 1
pinlabel=A9
T 450 3700 5 8 0 1 0 2 1
pintype=in
}
P 2200 3700 1900 3700 1 0 0
{
T 2000 3750 5 8 1 1 0 0 1
pinnumber=110
T 2000 3650 5 8 0 1 0 2 1
pinseq=110
T 1850 3700 9 8 1 1 0 6 1
pinlabel=BA1
T 1850 3700 5 8 0 1 0 8 1
pintype=in
}
P 100 3500 400 3500 1 0 0
{
T 300 3550 5 8 1 1 0 6 1
pinnumber=111
T 300 3450 5 8 0 1 0 8 1
pinseq=111
T 450 3500 9 8 1 1 0 0 1
pinlabel=A10
T 450 3500 5 8 0 1 0 2 1
pintype=in
}
P 2200 3500 1900 3500 1 0 0
{
T 2000 3550 5 8 1 1 0 0 1
pinnumber=112
T 2000 3450 5 8 0 1 0 2 1
pinseq=112
T 1850 3500 9 8 1 1 0 6 1
pinlabel=A11
T 1850 3500 5 8 0 1 0 8 1
pintype=in
}
P 100 3300 400 3300 1 0 0
{
T 300 3350 5 8 1 1 0 6 1
pinnumber=113
T 300 3250 5 8 0 1 0 8 1
pinseq=113
T 450 3300 9 8 1 1 0 0 1
pinlabel=VDD
T 450 3300 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 3300 1900 3300 1 0 0
{
T 2000 3350 5 8 1 1 0 0 1
pinnumber=114
T 2000 3250 5 8 0 1 0 2 1
pinseq=114
T 1850 3300 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 3300 5 8 0 1 0 8 1
pintype=pwr
}
P 100 3100 400 3100 1 0 0
{
T 300 3150 5 8 1 1 0 6 1
pinnumber=115
T 300 3050 5 8 0 1 0 8 1
pinseq=115
T 450 3100 9 8 1 1 0 0 1
pinlabel=DQMB2
T 450 3100 5 8 0 1 0 2 1
pintype=in
}
P 2200 3100 1900 3100 1 0 0
{
T 2000 3150 5 8 1 1 0 0 1
pinnumber=116
T 2000 3050 5 8 0 1 0 2 1
pinseq=116
T 1850 3100 9 8 1 1 0 6 1
pinlabel=DQMB6
T 1850 3100 5 8 0 1 0 8 1
pintype=in
}
P 100 2900 400 2900 1 0 0
{
T 300 2950 5 8 1 1 0 6 1
pinnumber=117
T 300 2850 5 8 0 1 0 8 1
pinseq=117
T 450 2900 9 8 1 1 0 0 1
pinlabel=DQMB3
T 450 2900 5 8 0 1 0 2 1
pintype=in
}
P 2200 2900 1900 2900 1 0 0
{
T 2000 2950 5 8 1 1 0 0 1
pinnumber=118
T 2000 2850 5 8 0 1 0 2 1
pinseq=118
T 1850 2900 9 8 1 1 0 6 1
pinlabel=DQMB7
T 1850 2900 5 8 0 1 0 8 1
pintype=in
}
P 100 2700 400 2700 1 0 0
{
T 300 2750 5 8 1 1 0 6 1
pinnumber=119
T 300 2650 5 8 0 1 0 8 1
pinseq=119
T 450 2700 9 8 1 1 0 0 1
pinlabel=VSS
T 450 2700 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 2700 1900 2700 1 0 0
{
T 2000 2750 5 8 1 1 0 0 1
pinnumber=120
T 2000 2650 5 8 0 1 0 2 1
pinseq=120
T 1850 2700 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 2700 5 8 0 1 0 8 1
pintype=pwr
}
P 100 2500 400 2500 1 0 0
{
T 300 2550 5 8 1 1 0 6 1
pinnumber=121
T 300 2450 5 8 0 1 0 8 1
pinseq=121
T 450 2500 9 8 1 1 0 0 1
pinlabel=DQ24
T 450 2500 5 8 0 1 0 2 1
pintype=io
}
P 2200 2500 1900 2500 1 0 0
{
T 2000 2550 5 8 1 1 0 0 1
pinnumber=122
T 2000 2450 5 8 0 1 0 2 1
pinseq=122
T 1850 2500 9 8 1 1 0 6 1
pinlabel=DQ56
T 1850 2500 5 8 0 1 0 8 1
pintype=io
}
P 100 2300 400 2300 1 0 0
{
T 300 2350 5 8 1 1 0 6 1
pinnumber=123
T 300 2250 5 8 0 1 0 8 1
pinseq=123
T 450 2300 9 8 1 1 0 0 1
pinlabel=DQ25
T 450 2300 5 8 0 1 0 2 1
pintype=io
}
P 2200 2300 1900 2300 1 0 0
{
T 2000 2350 5 8 1 1 0 0 1
pinnumber=124
T 2000 2250 5 8 0 1 0 2 1
pinseq=124
T 1850 2300 9 8 1 1 0 6 1
pinlabel=DQ57
T 1850 2300 5 8 0 1 0 8 1
pintype=io
}
P 100 2100 400 2100 1 0 0
{
T 300 2150 5 8 1 1 0 6 1
pinnumber=125
T 300 2050 5 8 0 1 0 8 1
pinseq=125
T 450 2100 9 8 1 1 0 0 1
pinlabel=DQ26
T 450 2100 5 8 0 1 0 2 1
pintype=io
}
P 2200 2100 1900 2100 1 0 0
{
T 2000 2150 5 8 1 1 0 0 1
pinnumber=126
T 2000 2050 5 8 0 1 0 2 1
pinseq=126
T 1850 2100 9 8 1 1 0 6 1
pinlabel=DQ58
T 1850 2100 5 8 0 1 0 8 1
pintype=io
}
P 100 1900 400 1900 1 0 0
{
T 300 1950 5 8 1 1 0 6 1
pinnumber=127
T 300 1850 5 8 0 1 0 8 1
pinseq=127
T 450 1900 9 8 1 1 0 0 1
pinlabel=DQ27
T 450 1900 5 8 0 1 0 2 1
pintype=io
}
P 2200 1900 1900 1900 1 0 0
{
T 2000 1950 5 8 1 1 0 0 1
pinnumber=128
T 2000 1850 5 8 0 1 0 2 1
pinseq=128
T 1850 1900 9 8 1 1 0 6 1
pinlabel=DQ59
T 1850 1900 5 8 0 1 0 8 1
pintype=io
}
P 100 1700 400 1700 1 0 0
{
T 300 1750 5 8 1 1 0 6 1
pinnumber=129
T 300 1650 5 8 0 1 0 8 1
pinseq=129
T 450 1700 9 8 1 1 0 0 1
pinlabel=VDD
T 450 1700 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 1700 1900 1700 1 0 0
{
T 2000 1750 5 8 1 1 0 0 1
pinnumber=130
T 2000 1650 5 8 0 1 0 2 1
pinseq=130
T 1850 1700 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 1700 5 8 0 1 0 8 1
pintype=pwr
}
P 100 1500 400 1500 1 0 0
{
T 300 1550 5 8 1 1 0 6 1
pinnumber=131
T 300 1450 5 8 0 1 0 8 1
pinseq=131
T 450 1500 9 8 1 1 0 0 1
pinlabel=DQ28
T 450 1500 5 8 0 1 0 2 1
pintype=io
}
P 2200 1500 1900 1500 1 0 0
{
T 2000 1550 5 8 1 1 0 0 1
pinnumber=132
T 2000 1450 5 8 0 1 0 2 1
pinseq=132
T 1850 1500 9 8 1 1 0 6 1
pinlabel=DQ60
T 1850 1500 5 8 0 1 0 8 1
pintype=io
}
P 100 1300 400 1300 1 0 0
{
T 300 1350 5 8 1 1 0 6 1
pinnumber=133
T 300 1250 5 8 0 1 0 8 1
pinseq=133
T 450 1300 9 8 1 1 0 0 1
pinlabel=DQ29
T 450 1300 5 8 0 1 0 2 1
pintype=io
}
P 2200 1300 1900 1300 1 0 0
{
T 2000 1350 5 8 1 1 0 0 1
pinnumber=134
T 2000 1250 5 8 0 1 0 2 1
pinseq=134
T 1850 1300 9 8 1 1 0 6 1
pinlabel=DQ61
T 1850 1300 5 8 0 1 0 8 1
pintype=io
}
P 100 1100 400 1100 1 0 0
{
T 300 1150 5 8 1 1 0 6 1
pinnumber=135
T 300 1050 5 8 0 1 0 8 1
pinseq=135
T 450 1100 9 8 1 1 0 0 1
pinlabel=DQ30
T 450 1100 5 8 0 1 0 2 1
pintype=io
}
P 2200 1100 1900 1100 1 0 0
{
T 2000 1150 5 8 1 1 0 0 1
pinnumber=136
T 2000 1050 5 8 0 1 0 2 1
pinseq=136
T 1850 1100 9 8 1 1 0 6 1
pinlabel=DQ62
T 1850 1100 5 8 0 1 0 8 1
pintype=io
}
P 100 900 400 900 1 0 0
{
T 300 950 5 8 1 1 0 6 1
pinnumber=137
T 300 850 5 8 0 1 0 8 1
pinseq=137
T 450 900 9 8 1 1 0 0 1
pinlabel=DQ31
T 450 900 5 8 0 1 0 2 1
pintype=io
}
P 2200 900 1900 900 1 0 0
{
T 2000 950 5 8 1 1 0 0 1
pinnumber=138
T 2000 850 5 8 0 1 0 2 1
pinseq=138
T 1850 900 9 8 1 1 0 6 1
pinlabel=DQ63
T 1850 900 5 8 0 1 0 8 1
pintype=io
}
P 100 700 400 700 1 0 0
{
T 300 750 5 8 1 1 0 6 1
pinnumber=139
T 300 650 5 8 0 1 0 8 1
pinseq=139
T 450 700 9 8 1 1 0 0 1
pinlabel=VSS
T 450 700 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 700 1900 700 1 0 0
{
T 2000 750 5 8 1 1 0 0 1
pinnumber=140
T 2000 650 5 8 0 1 0 2 1
pinseq=140
T 1850 700 9 8 1 1 0 6 1
pinlabel=VSS
T 1850 700 5 8 0 1 0 8 1
pintype=pwr
}
P 100 500 400 500 1 0 0
{
T 300 550 5 8 1 1 0 6 1
pinnumber=141
T 300 450 5 8 0 1 0 8 1
pinseq=141
T 450 500 9 8 1 1 0 0 1
pinlabel=SDA
T 450 500 5 8 0 1 0 2 1
pintype=io
}
P 2200 500 1900 500 1 0 0
{
T 2000 550 5 8 1 1 0 0 1
pinnumber=142
T 2000 450 5 8 0 1 0 2 1
pinseq=142
T 1850 500 9 8 1 1 0 6 1
pinlabel=SCL
T 1850 500 5 8 0 1 0 8 1
pintype=in
}
P 100 300 400 300 1 0 0
{
T 300 350 5 8 1 1 0 6 1
pinnumber=143
T 300 250 5 8 0 1 0 8 1
pinseq=143
T 450 300 9 8 1 1 0 0 1
pinlabel=VDD
T 450 300 5 8 0 1 0 2 1
pintype=pwr
}
P 2200 300 1900 300 1 0 0
{
T 2000 350 5 8 1 1 0 0 1
pinnumber=144
T 2000 250 5 8 0 1 0 2 1
pinseq=144
T 1850 300 9 8 1 1 0 6 1
pinlabel=VDD
T 1850 300 5 8 0 1 0 8 1
pintype=pwr
}
B 400 100 1500 14600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1900 14800 8 10 1 1 0 6 1
refdes=J?
T 400 14800 9 10 1 0 0 0 1
sodimm144
T 400 15000 5 10 0 0 0 0 1
device=sodimm144
T 400 15200 5 10 0 0 0 0 1
author=David Carr
T 400 15400 5 10 0 0 0 0 1
documentation=null
T 400 15600 5 10 0 0 0 0 1
description=144 pin SODIMM socket (SDR)
T 400 15800 5 10 0 0 0 0 1
numslots=0

Attachment: ram.ps
Description: PostScript document

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