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Re: gEDA-user: using TI spice models
Another way to check your results is to read your netlist into LTSpice
and/or Gnucap and run your sim using it. Indeed, since Gnucap is a
completely different simulator, comparing ngspice to Gnucap is a good
robustness test. If you get same result (likely), then the problem is
your circuit, not your sim.
Stuart
>
> Stuart,
>
> Thanks for your sugguestion, that worked fine. Unfortunately, I'm not
> getting results in line with what I expect. Should I be concerned about
> the other warnings?
>
> Thanks for your time,
> David Carr
>
> Stuart Brorson wrote:
>
> >I am not sure if ngspice recognizes "+" and "-" as valid characers, at
> >least in the name of a component. Your model incorporates current
> >sources ib+ and ib-. Try changing them to ib_p and ib_m.
> >
> >Stuart
> >
> >
> >
> >
> >
> >>This is a multi-part message in MIME format.
> >>--------------000403090204010705010606
> >>Content-Type: text/plain; charset=ISO-8859-1
> >>Content-Transfer-Encoding: 7bit
> >>
> >>I'm trying to use ngspice to model a TI opamp. When I load the netlist
> >>though, ngspice says:
> >>
> >>ngspice 46 -> source test.net
> >>
> >>Circuit: * gnetlist -g spice-sdb -o test.net test.sch
> >>
> >>Warning -- Level not specified on line "kf=1e-11"
> >>Using level 1.
> >>Warning -- Level not specified on line "kf=1e-11"
> >>Using level 1.
> >>Warning -- Level not specified on line ""
> >>Using level 1.
> >>Warning -- Level not specified on line ""
> >>Using level 1.
> >>Error on line 41 : i:101:b+ 1 0 8u
> >> unknown parameter (8u)
> >>Error on line 42 : i:101:b- 2 0 8u
> >> device already exists, existing one being used
> >>
> >> unknown parameter (8u)
> >>
> >>I'm a complete spice neophyte trying to follow Suart's tutorial so this
> >>very well could be my fault. I'll attach the schematic, spice netlist
> >>and the models.
> >>
> >>Thanks for looking at this,
> >>David Carr
> >>
> >>
> >>--------------000403090204010705010606
> >>Content-Type: text/plain;
> >> name="test.net"
> >>Content-Transfer-Encoding: 7bit
> >>Content-Disposition: inline;
> >> filename="test.net"
> >>
> >>* gnetlist -g spice-sdb -o test.net test.sch
> >>*********************************************************
> >>* Spice file generated by gnetlist *
> >>* spice-sdb version 12.27.2005 by SDB -- *
> >>* provides advanced spice netlisting capability. *
> >>* Documentation at http://www.brorson.com/gEDA/SPICE/ *
> >>*********************************************************
> >>*vvvvvvvv Included SPICE model from ths4513.sub vvvvvvvv
> >>* THS4513 SUBCIRCUIT Rev-
> >>* FULLY DIFFERENTIAL HIGH SPEED MONLITHIC OPERATIONAL AMPLIFIER
> >>* WRITTEN 02-7-06
> >>* THIS MODEL SIMULATES TYPICAL VALUES FOR THE FOLLOWING:
> >>* FREQUENCY RESPONSE OF THE MAIN DIFFERENTIAL AMP, OUTPUT VOLTAGE LIMIT,
> >>* INPUT VOLTAGE NOISE, INPUT BIAS CURRENT, INPUT OFFSET VOLTAGE, CM SET POINT, OFFSET, AND BANDWIDTH
> >>* THIS MODEL WILL NOT PROVIDE ACCURATE SIMULATION OF: OUTPUT LOADING EFFECTS, SLEW RATE, SETTLING TIME
> >>* OUTPUT IMPEDANCE, INPUT CURRENT NOISE, DISTORTION, INPUT OFFSET vs INPUT COMMON-MODE VOLTAGE, CMRR AND PSRR
> >>* IN PSPICE THIS MODEL WILL NOT CONVERGE IN TRANSIENT ANALYSIS USING PULSES THAT CAUSE GREATER THAN 4000V/us SLEW RATE
> >>
> >>*$
> >>.SUBCKT THS4513 IN+ IN- Vs+ Vs- OUT- OUT+ CM
> >>
> >>*INPUT*
> >>Q9 Vs- 001 005 PNP_IN 2.5
> >>Q10 Vs- IN- 031 PNP_IN 2.505
> >>Q11 Vs+ IN- 006 NPN_IN 2.5
> >>Q12 Vs+ 001 002 NPN_IN 2.495
> >>Q19 039 005 008 NPN 5.198
> >>Q20 038 031 009 NPN 5
> >>Q21 033 006 009 PNP 5.198
> >>Q22 035 002 008 PNP 5
> >>R1 009 008 90
> >>VI1 002 003 0.69995
> >>VI2 004 005 0.701
> >>VI3 006 007 0.701
> >>VI10 036 031 0.70005
> >>R20 036 Vs+ 2.7k
> >>R21 004 Vs+ 2.7k
> >>R22 Vs- 003 2.7k
> >>R23 Vs- 007 2.7k
> >>C1 0 001 0.3p
> >>C2 0 IN- 0.3p
> >>V1 001 IN+ 000u
> >>IB+ IN+ 0 8u
> >>IB- IN- 0 8u
> >>
> >>*HIGH Z NODE*
> >>Q23 041 041 039 PNP 5
> >>Q24 027 041 038 PNP 5
> >>Q17 037 037 038 PNP 5
> >>Q18 029 037 039 PNP 5
> >>Q15 032 032 033 NPN 5
> >>Q16 034 034 035 NPN 5
> >>Q14 029 032 035 NPN 5
> >>Q13 027 034 033 NPN 5
> >>I8 Vs+ 032 DC 750u
> >>I9 Vs+ 034 DC 750u
> >>I11 037 Vs- DC 750u
> >>I12 041 Vs- DC 750u
> >>R30 029 027 0.5meg
> >>C5 029 027 0.7p
> >>R16 038 Vs+ 500
> >>R17 039 Vs+ 500
> >>R18 038 Vs+ 500
> >>R19 039 Vs+ 500
> >>R24 Vs- 035 500
> >>R25 Vs- 033 500
> >>R26 Vs- 035 500
> >>R27 Vs- 033 500
> >>
> >>*VOLTAGE LIMIT*
> >>Q116 027 027 128 NPN 5
> >>V116 Vs+ 128 1.75
> >>Q118 027 027 138 PNP 5
> >>V118 138 Vs- 1.75
> >>Q216 029 029 228 NPN 5
> >>V216 Vs+ 228 1.75
> >>Q218 029 029 238 PNP 5
> >>V218 238 Vs- 1.75
> >>RQ Vs+ Vs- 475
> >>
> >>*FREQUENCY SHAPING*
> >>E2 028 0 027 0 1
> >>E3 030 0 029 0 1
> >>C3 0 024 3p
> >>C4 0 017 3p
> >>L1 025 028 2n
> >>L2 030 026 2n
> >>R10 024 025 25
> >>R11 017 026 25
> >>
> >>*OUTPUT BUFFER*
> >>Q1 Vs+ 012 013 NPN 50
> >>Q2 Vs- 015 016 PNP 50
> >>Q3 Vs+ 017 015 NPN 13
> >>Q4 Vs- 017 012 PNP 13
> >>Q5 Vs+ 019 020 NPN 50
> >>Q6 Vs- 021 023 PNP 50
> >>Q7 Vs+ 024 021 NPN 13
> >>Q8 Vs- 024 019 PNP 13
> >>I4 011 012 DC 2m
> >>I5 015 014 DC 2m
> >>I6 018 019 DC 2m
> >>I7 021 022 DC 2m
> >>R4 Vs- 014 100
> >>R7 018 Vs+ 100
> >>R12 011 Vs+ 100
> >>R13 Vs- 022 100
> >>R5 OUT- 013 1
> >>R6 016 OUT- 1
> >>R8 OUT+ 020 1
> >>R9 023 OUT+ 1
> >>
> >>*CM CIRCUIT*
> >>R2 OUT+ 010 10k
> >>R3 010 OUT- 10k
> >>*C102 OUT+ 010 100p
> >>*C103 010 OUT- 100p
> >>R114 CM CM2 100
> >>C114 CM2 0 2.3p
> >>R14 Vs+ CM2 50k
> >>R15 Vs- CM2 50k
> >>V3 043 CM2 3m
> >>F2 041 Vs- VF2 1
> >>VF2 040 Vs- 0V
> >>F1 037 Vs- VF1 1
> >>VF1 042 040 0V
> >>G1 042 Vs+ 010 043 .002
> >>*R100 042 0 1meg
> >>*C100 042 0 10p
> >>
> >>.MODEL NPN_IN NPN KF=1E-11
> >>.MODEL PNP_IN PNP KF=1E-11
> >>.MODEL NPN NPN
> >>.MODEL PNP PNP
> >>.ENDS
> >>
> >>
> >>
> >>*$
> >>*^^^^^^^^ End of included SPICE model from ths4513.sub ^^^^^^^^
> >>*
> >>*============== Begin SPICE netlist of main design ============
> >>C102 V2 0 12pF
> >>R101 1 3 340
> >>C101 V1 0 12pF
> >>X101 1 2 Vcc -Vcc 4 3 0 ths4513
> >>R106 4 V2 100
> >>R105 3 V1 100
> >>R104 5 1 340
> >>V103 5 0 AC
> >>R103 0 2 340
> >>V102 Vcc 0 DC 1.66V
> >>R102 2 4 340
> >>V101 0 -Vcc DC 1.66V
> >>.END
> >>
> >>--------------000403090204010705010606
> >>Content-Type: text/plain;
> >> name="test.sch"
> >>Content-Transfer-Encoding: 7bit
> >>Content-Disposition: inline;
> >> filename="test.sch"
> >>
> >>v 20060123 1
> >>C 45600 26300 1 0 0 ths4513.sym
> >>{
> >>T 46800 28200 5 10 1 1 0 0 1
> >>refdes=X101
> >>T 47100 28200 5 10 1 1 0 0 1
> >>value=ths4513
> >>T 46800 27200 5 10 1 1 0 0 1
> >>file=ths4513.sub
> >>}
> >>C 44500 30800 1 0 0 vdc-1.sym
> >>{
> >>T 45200 31450 5 10 1 1 0 0 1
> >>refdes=V101
> >>T 45200 31250 5 10 1 1 0 0 1
> >>value=DC 1.66V
> >>}
> >>C 44500 32300 1 0 0 vdc-1.sym
> >>{
> >>T 45200 32950 5 10 1 1 0 0 1
> >>refdes=V102
> >>T 45200 32750 5 10 1 1 0 0 1
> >>value=DC 1.66V
> >>}
> >>C 45200 31800 1 0 0 gnd-1.sym
> >>C 44500 30100 1 0 0 vcc-minus-1.sym
> >>C 44600 33600 1 0 0 vcc-2.sym
> >>N 44800 33500 44800 33600 4
> >>N 45300 32100 44800 32100 4
> >>N 44800 32000 44800 32300 4
> >>N 44800 30700 44800 30800 4
> >>C 46400 28400 1 0 0 vcc-2.sym
> >>C 46300 26600 1 0 0 vcc-minus-1.sym
> >>N 46600 27200 46600 27300 4
> >>N 46600 28300 46600 28400 4
> >>C 44600 27900 1 270 0 gnd-1.sym
> >>N 44900 27800 46100 27800 4
> >>C 46200 29300 1 0 0 resistor-1.sym
> >>{
> >>T 46400 29600 5 10 1 1 0 0 1
> >>refdes=R101
> >>T 46500 29100 5 10 1 1 0 0 1
> >>value=340
> >>}
> >>C 42100 26700 1 0 0 vsin-1.sym
> >>{
> >>T 42800 27350 5 10 1 1 0 0 1
> >>refdes=V103
> >>T 42800 27150 5 10 1 1 0 0 1
> >>value=AC
> >>}
> >>N 45900 28100 46100 28100 4
> >>N 45900 27500 46100 27500 4
> >>N 46200 26100 46000 26100 4
> >>N 46000 26100 46000 27500 4
> >>N 46200 29400 46000 29400 4
> >>N 46000 29400 46000 28100 4
> >>C 44700 27100 1 0 0 gnd-1.sym
> >>N 44800 27400 44800 27500 4
> >>N 44800 27500 45000 27500 4
> >>C 42300 26200 1 0 0 gnd-1.sym
> >>N 42400 26500 42400 26700 4
> >>N 45000 28100 42400 28100 4
> >>N 42400 28100 42400 27900 4
> >>N 47100 26100 47600 26100 4
> >>N 47600 26100 47600 27700 4
> >>N 47600 27700 47100 27700 4
> >>N 47600 27900 47600 29400 4
> >>N 47600 29400 47100 29400 4
> >>C 46200 26000 1 0 0 resistor-1.sym
> >>{
> >>T 46400 26300 5 10 1 1 0 0 1
> >>refdes=R102
> >>T 46500 25800 5 10 1 1 0 0 1
> >>value=340
> >>}
> >>C 45000 27400 1 0 0 resistor-1.sym
> >>{
> >>T 45200 27700 5 10 1 1 0 0 1
> >>refdes=R103
> >>T 45300 27200 5 10 1 1 0 0 1
> >>value=340
> >>}
> >>C 45000 28000 1 0 0 resistor-1.sym
> >>{
> >>T 45200 28300 5 10 1 1 0 0 1
> >>refdes=R104
> >>T 45300 27800 5 10 1 1 0 0 1
> >>value=340
> >>}
> >>C 48100 28300 1 0 0 resistor-1.sym
> >>{
> >>T 48300 28600 5 10 1 1 0 0 1
> >>refdes=R105
> >>T 48400 28100 5 10 1 1 0 0 1
> >>value=100
> >>}
> >>C 48100 27100 1 0 0 resistor-1.sym
> >>{
> >>T 48300 27400 5 10 1 1 0 0 1
> >>refdes=R106
> >>T 48400 26900 5 10 1 1 0 0 1
> >>value=100
> >>}
> >>N 48100 27200 47600 27200 4
> >>N 47100 27900 47600 27900 4
> >>N 48100 28400 47600 28400 4
> >>C 49400 28200 1 0 0 capacitor-1.sym
> >>{
> >>T 49600 28700 5 10 1 1 0 0 1
> >>refdes=C101
> >>T 49600 29100 5 10 0 0 0 0 1
> >>symversion=0.1
> >>T 49700 28000 5 10 1 1 0 0 1
> >>value=12pF
> >>}
> >>N 49000 28400 49400 28400 4
> >>{
> >>T 49000 28500 5 10 1 1 0 0 1
> >>netname=V1
> >>}
> >>C 50300 27900 1 0 0 gnd-1.sym
> >>N 50300 28400 50400 28400 4
> >>N 50400 28400 50400 28200 4
> >>C 49400 27000 1 0 0 capacitor-1.sym
> >>{
> >>T 49600 27500 5 10 1 1 0 0 1
> >>refdes=C102
> >>T 49600 27900 5 10 0 0 0 0 1
> >>symversion=0.1
> >>T 49700 26800 5 10 1 1 0 0 1
> >>value=12pF
> >>}
> >>C 50300 26700 1 0 0 gnd-1.sym
> >>N 50300 27200 50400 27200 4
> >>N 50400 27200 50400 27000 4
> >>N 49000 27200 49400 27200 4
> >>{
> >>T 49000 27300 5 10 1 1 0 0 1
> >>netname=V2
> >>}
> >>
> >>--------------000403090204010705010606
> >>Content-Type: text/plain;
> >> name="ths4513.sub"
> >>Content-Transfer-Encoding: 7bit
> >>Content-Disposition: inline;
> >> filename="ths4513.sub"
> >>
> >>* THS4513 SUBCIRCUIT Rev-
> >>* FULLY DIFFERENTIAL HIGH SPEED MONLITHIC OPERATIONAL AMPLIFIER
> >>* WRITTEN 02-7-06
> >>* THIS MODEL SIMULATES TYPICAL VALUES FOR THE FOLLOWING:
> >>* FREQUENCY RESPONSE OF THE MAIN DIFFERENTIAL AMP, OUTPUT VOLTAGE LIMIT,
> >>* INPUT VOLTAGE NOISE, INPUT BIAS CURRENT, INPUT OFFSET VOLTAGE, CM SET POINT, OFFSET, AND BANDWIDTH
> >>* THIS MODEL WILL NOT PROVIDE ACCURATE SIMULATION OF: OUTPUT LOADING EFFECTS, SLEW RATE, SETTLING TIME
> >>* OUTPUT IMPEDANCE, INPUT CURRENT NOISE, DISTORTION, INPUT OFFSET vs INPUT COMMON-MODE VOLTAGE, CMRR AND PSRR
> >>* IN PSPICE THIS MODEL WILL NOT CONVERGE IN TRANSIENT ANALYSIS USING PULSES THAT CAUSE GREATER THAN 4000V/us SLEW RATE
> >>
> >>*$
> >>.SUBCKT THS4513 IN+ IN- Vs+ Vs- OUT- OUT+ CM
> >>
> >>*INPUT*
> >>Q9 Vs- 001 005 PNP_IN 2.5
> >>Q10 Vs- IN- 031 PNP_IN 2.505
> >>Q11 Vs+ IN- 006 NPN_IN 2.5
> >>Q12 Vs+ 001 002 NPN_IN 2.495
> >>Q19 039 005 008 NPN 5.198
> >>Q20 038 031 009 NPN 5
> >>Q21 033 006 009 PNP 5.198
> >>Q22 035 002 008 PNP 5
> >>R1 009 008 90
> >>VI1 002 003 0.69995
> >>VI2 004 005 0.701
> >>VI3 006 007 0.701
> >>VI10 036 031 0.70005
> >>R20 036 Vs+ 2.7k
> >>R21 004 Vs+ 2.7k
> >>R22 Vs- 003 2.7k
> >>R23 Vs- 007 2.7k
> >>C1 0 001 0.3p
> >>C2 0 IN- 0.3p
> >>V1 001 IN+ 000u
> >>IB+ IN+ 0 8u
> >>IB- IN- 0 8u
> >>
> >>*HIGH Z NODE*
> >>Q23 041 041 039 PNP 5
> >>Q24 027 041 038 PNP 5
> >>Q17 037 037 038 PNP 5
> >>Q18 029 037 039 PNP 5
> >>Q15 032 032 033 NPN 5
> >>Q16 034 034 035 NPN 5
> >>Q14 029 032 035 NPN 5
> >>Q13 027 034 033 NPN 5
> >>I8 Vs+ 032 DC 750u
> >>I9 Vs+ 034 DC 750u
> >>I11 037 Vs- DC 750u
> >>I12 041 Vs- DC 750u
> >>R30 029 027 0.5meg
> >>C5 029 027 0.7p
> >>R16 038 Vs+ 500
> >>R17 039 Vs+ 500
> >>R18 038 Vs+ 500
> >>R19 039 Vs+ 500
> >>R24 Vs- 035 500
> >>R25 Vs- 033 500
> >>R26 Vs- 035 500
> >>R27 Vs- 033 500
> >>
> >>*VOLTAGE LIMIT*
> >>Q116 027 027 128 NPN 5
> >>V116 Vs+ 128 1.75
> >>Q118 027 027 138 PNP 5
> >>V118 138 Vs- 1.75
> >>Q216 029 029 228 NPN 5
> >>V216 Vs+ 228 1.75
> >>Q218 029 029 238 PNP 5
> >>V218 238 Vs- 1.75
> >>RQ Vs+ Vs- 475
> >>
> >>*FREQUENCY SHAPING*
> >>E2 028 0 027 0 1
> >>E3 030 0 029 0 1
> >>C3 0 024 3p
> >>C4 0 017 3p
> >>L1 025 028 2n
> >>L2 030 026 2n
> >>R10 024 025 25
> >>R11 017 026 25
> >>
> >>*OUTPUT BUFFER*
> >>Q1 Vs+ 012 013 NPN 50
> >>Q2 Vs- 015 016 PNP 50
> >>Q3 Vs+ 017 015 NPN 13
> >>Q4 Vs- 017 012 PNP 13
> >>Q5 Vs+ 019 020 NPN 50
> >>Q6 Vs- 021 023 PNP 50
> >>Q7 Vs+ 024 021 NPN 13
> >>Q8 Vs- 024 019 PNP 13
> >>I4 011 012 DC 2m
> >>I5 015 014 DC 2m
> >>I6 018 019 DC 2m
> >>I7 021 022 DC 2m
> >>R4 Vs- 014 100
> >>R7 018 Vs+ 100
> >>R12 011 Vs+ 100
> >>R13 Vs- 022 100
> >>R5 OUT- 013 1
> >>R6 016 OUT- 1
> >>R8 OUT+ 020 1
> >>R9 023 OUT+ 1
> >>
> >>*CM CIRCUIT*
> >>R2 OUT+ 010 10k
> >>R3 010 OUT- 10k
> >>*C102 OUT+ 010 100p
> >>*C103 010 OUT- 100p
> >>R114 CM CM2 100
> >>C114 CM2 0 2.3p
> >>R14 Vs+ CM2 50k
> >>R15 Vs- CM2 50k
> >>V3 043 CM2 3m
> >>F2 041 Vs- VF2 1
> >>VF2 040 Vs- 0V
> >>F1 037 Vs- VF1 1
> >>VF1 042 040 0V
> >>G1 042 Vs+ 010 043 .002
> >>*R100 042 0 1meg
> >>*C100 042 0 10p
> >>
> >>.MODEL NPN_IN NPN KF=1E-11
> >>.MODEL PNP_IN PNP KF=1E-11
> >>.MODEL NPN NPN
> >>.MODEL PNP PNP
> >>.ENDS
> >>
> >>
> >>
> >>*$
> >>
> >>--------------000403090204010705010606
> >>Content-Type: text/plain;
> >> name="ths4513.sym"
> >>Content-Transfer-Encoding: 7bit
> >>Content-Disposition: inline;
> >> filename="ths4513.sym"
> >>
> >>v 20060123 1
> >>L 700 1900 700 1100 3 0 0 0 -1 -1
> >>L 800 1850 800 1750 3 0 0 0 -1 -1
> >>L 750 1800 850 1800 3 0 0 0 -1 -1
> >>L 750 1200 850 1200 3 0 0 0 -1 -1
> >>P 500 1800 700 1800 1 0 0
> >>{
> >>T 650 1850 5 8 1 1 0 6 1
> >>pinnumber=1
> >>T 700 1750 5 8 0 1 0 8 1
> >>pinseq=1
> >>T 750 1800 5 8 0 1 0 0 1
> >>pinlabel=IN+
> >>T 750 1800 5 8 0 1 0 2 1
> >>pintype=in
> >>}
> >>P 500 1200 700 1200 1 0 0
> >>{
> >>T 650 1250 5 8 1 1 0 6 1
> >>pinnumber=2
> >>T 650 1150 5 8 0 1 0 8 1
> >>pinseq=2
> >>T 750 1200 5 8 0 1 0 0 1
> >>pinlabel=IN-
> >>T 750 1200 5 8 0 1 0 2 1
> >>pintype=in
> >>}
> >>P 1300 1600 1500 1600 1 0 1
> >>{
> >>T 1350 1650 5 8 1 1 0 0 1
> >>pinnumber=6
> >>T 1350 1550 5 8 0 1 0 2 1
> >>pinseq=6
> >>T 1250 1600 5 8 0 1 0 6 1
> >>pinlabel=OUT+
> >>T 1250 1600 5 8 0 1 0 8 1
> >>pintype=out
> >>}
> >>P 1000 1800 1000 2000 1 0 1
> >>{
> >>T 1050 1850 5 8 1 1 0 0 1
> >>pinnumber=3
> >>T 1050 1850 5 8 0 1 0 2 1
> >>pinseq=3
> >>T 1000 1750 5 8 0 1 0 5 1
> >>pinlabel=Vs+
> >>T 1000 1650 5 8 0 1 0 5 1
> >>pintype=pwr
> >>}
> >>P 1000 1200 1000 1000 1 0 1
> >>{
> >>T 1050 1100 5 8 1 1 0 0 1
> >>pinnumber=4
> >>T 1050 1100 5 8 0 1 0 2 1
> >>pinseq=4
> >>T 1000 1250 5 8 0 1 0 3 1
> >>pinlabel=Vs-
> >>T 1000 1350 5 8 0 1 0 3 1
> >>pintype=pwr
> >>}
> >>L 700 1900 700 2000 3 0 0 0 -1 -1
> >>L 700 1100 700 1000 3 0 0 0 -1 -1
> >>L 700 1000 1400 1500 3 0 0 0 -1 -1
> >>L 1400 1500 700 2000 3 0 0 0 -1 -1
> >>T 1200 1900 8 10 1 1 0 0 1
> >>refdes=X?
> >>P 1300 1400 1500 1400 1 0 1
> >>{
> >>T 1350 1250 5 8 1 1 0 0 1
> >>pinnumber=5
> >>T 1350 1350 5 8 0 1 0 2 1
> >>pinseq=5
> >>T 1250 1400 5 8 0 1 0 6 1
> >>pinlabel=OUT-
> >>T 1250 1400 5 8 0 1 0 8 1
> >>pintype=out
> >>}
> >>P 700 1500 500 1500 1 0 1
> >>{
> >>T 650 1550 5 8 1 1 0 6 1
> >>pinnumber=7
> >>T 650 1450 5 8 0 1 0 8 1
> >>pinseq=7
> >>T 750 1500 5 8 0 1 0 0 1
> >>pinlabel=CM
> >>T 750 1500 5 8 0 1 0 2 1
> >>pintype=in
> >>}
> >>T 750 1500 9 8 1 0 0 0 1
> >>CM
> >>T 68100 47500 8 10 0 1 0 0 1
> >>device=IC
> >>T 1200 1100 9 10 1 0 0 0 1
> >>Spice
> >>
> >>--------------000403090204010705010606--
> >>
> >>
> >>
>
>