gEDA-user: fpga.tgt: IVL_LPM_CMP_GE not supported by this target

[Mark Allyn <allyn@xxxxxxxx>]

Does anyone know if this is really an error or is it just
a shortcomming of the fpga type in the iverilog compiler?

I am doing designs which I eventually want to impliment on
altera.

Here is the snippit of code that caused this:

============================================
module tester (clk,ctr);
input clk;
output [7:0] ctr;
reg [7:0] ctr;

always @ (posedge clk)
begin
  if (ctr <= 9) begin
    ctr <= ctr + 1;
  end else begin
    ctr <= 0;
  end
end

endmodule
=============================================

I anticipate having several comparisons in my
circuit as it will be a demultiplexer for packets

Thank you

Mark Allyn