Re: gEDA-user: fpga.tgt: IVL_LPM_CMP_GE not supported by this target

[Stephen Williams <steve@xxxxxxxxxx>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


It is a shortcoming of the fpga code generator. Your code is probably
synthesizing correctly, but the fpga target (at least for the part
family you are using) does not have the code generator support yet.

That is what the message is saying.

Mark Allyn wrote:
> Does anyone know if this is really an error or is it just
> a shortcomming of the fpga type in the iverilog compiler?
> 
> I am doing designs which I eventually want to impliment on
> altera.
> 
> Here is the snippit of code that caused this:
> 
> ============================================
> module tester (clk,ctr);
> input clk;
> output [7:0] ctr;
> reg [7:0] ctr;
> 
> always @ (posedge clk)
> begin
>   if (ctr <= 9) begin
>     ctr <= ctr + 1;
>   end else begin
>     ctr <= 0;
>   end
> end
> 
> endmodule
> =============================================
> 
> I anticipate having several comparisons in my
> circuit as it will be a demultiplexer for packets
> 
> Thank you
> 
> Mark Allyn
> 


- --
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.2.5 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

iD8DBQFEexwTrPt1Sc2b3ikRAqj6AJ9m7zE45ZsErGmCfGp6Ss435VDyfACgkFAZ
PUVSEJ+5jH3krM5tOpACj+w=
=HNMW
-----END PGP SIGNATURE-----