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Re: gEDA-user: Re: iverilog: Parameters of Parameters

On 30 Apr 2007, at 10:20:13 PM, Stephen Williams wrote:

I've looked at the thread in comp.lang.verilog. The parameter

definition circularity problem is nasty, but a carefully contained

extension (a la the way Modelsim handles it) seems plausible.

This is a good candidate for the Feature Request list, I think.


While I would like to see such a feature,
I've found that XST, the synthesis tool
from Xilinx, does not support it (even
though ModelSim apparently does).

I suppose, then, it would be a bad idea to
add to iverilog.

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