Stephen Williams wrote:
lingwitt-Bdlq13kUjeyLZ21kGMrzwg@public.gmane.org wrote:Basically, I'm whining for a feature.I've looked at the thread in comp.lang.verilog. The parameter definition circularity problem is nasty, but a carefully contained extension (a la the way Modelsim handles it) seems plausible. This is a good candidate for the Feature Request list, I think.
But it's not valid Verilog. If you start adding nice features that aren't in the LRM, and aren't supported in the reference compilers, where will it all end?
...in VHDL, perhaps? [sorry, couldn't resist... :)] _______________________________________________ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user