Re: gEDA-user: Does anybody know an open source vhdl-ams simulator?

[al davis <ad136@freeelectron.net>]

On Thursday 17 May 2007, Svenn Are Bjerkem wrote:
> I have just googled around for a vhdl-ams simulator, and I
> only find very expencive ones. Is it really no F/OSS vhdl-ams
> simulator out there?
>
> I know Al is working on Verilog-AMS in gnucap, but is that
> the only F/OSS Verilog-AMS initiative out there?

The difference is in the parser.  Both have essentially the same 
underlying algorithms.  Where you find one, eventually you will 
find the other.

There was a start from University of Cincinnati a few years ago.  
As far as I know, it was only a start, and has not been 
developed past the initial proof of concept.  According to its 
creator, the performance was very slow, and it was a subset.

That is the only one I know of.

If you want to help with gnucap, you can make it happen.

What the simulator takes directly will be determined by a 
plug-in. 

I am doing Verilog first because I see a higher demand for it, 
and because it is less verbose and so is a more reasonable 
replacement for the Spice format with manually generated 
netlists.

When the language plug-in mechanism is working, which will be 
soon, it is reasonable to do plug-ins for other languages.  
After doing the first one, I expect others such as VHDL to be 
easy.

What the simulator takes directly will always be a subset.  A 
more complete version of any language will use the model 
compiler.  Here too, I am doing Verilog first (actually second) 
because I see a higher demand, and it should be relatively 
simple to change the front-end to accept other languages that 
are similar in concept, such as VHDL.

The model compiler generates C++, which is then compiled into a 
model plug-in, that can be attached when needed.  Most of this 
part is already working.

I see needs for the following other formats:
VHDL
Spectre
MAST
Touchstone
PCB (without crosstalk)
gschem
QUCS
HSPICE
PSPICE
...

There are some others that need more than simple translation:
IBIS (90% done)
more detail from PCB (with crosstalk)
...

The simulator core is not locked into any language.  All will 
use plug-ins.  All that exist will be equal in the sense of 
using a similar plug-in, that stores in the same data 
structures.

Does anyone want to help???  What is needed is to make the 
plug-ins and compiler front-ends for the other languages.  
After the first one is solid, you can use it as a model to make 
others.

I see big opportunities here, but I can't do it alone.

al.



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