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Re: gEDA-user: PCB: How do I insert a new layer without breaking the layout?



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Hash: SHA1

Christoph Lechner wrote:
> I created my PCB file using gsch2pcb at the very beginning. I'll play
> around a little bit to find out why my PCB breaks while yours won't break.
Created a simple test case that reproduces the problem for me. Looks
like gsch2pcb does something that pcb dislikes.

For me it breaks when I open the file (created by gsch2pcb), add some
new layers and press 'o' to optimize rats. Please the the tar file tc.tgz.

When I start up pcb with a new file, doing some stuff, and then adding
some new layers it won't break. I just added two 1206 to a new PCB
(created by pcb) and a net (by drawing on the rats layer). Then I routed
the net by hand. Here adding some layers won't break it. File
'wontbreak.pcb'.

I'm still running the old geda 1.4.0.
PCB version 20091103 (but pcb-20081128 has the same behavior).

- - cl
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Attachment: tc.tgz
Description: application/compressed-tar

# release: pcb 20091103
# date:    Sat May  8 16:25:34 2010
# user:    cl (,,,)
# host:    localhost.localdomain

# To read pcb files, the pcb version (or the cvs source date) must be >= the file version
FileVersion[20070407]

PCB["" 50000 50000]

Grid[1000.000000 0 0 0]
Cursor[0 0 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[699 400 800 800 1500 1000]
Flags("nameonpcb,uniquename,clearnew,snappin")
Groups("1,c:2,s:3:4:5:6:7:8")
Styles["Signal,1000,3600,2000,1000:Power,2500,6000,3500,1000:Fat,4000,6000,3500,1000:Skinny,600,2402,1181,600"]

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Element["" "Standard SMT resistor, capacitor etc" "R1" "1206" 15000 9000 -3150 -3150 0 100 ""]
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Element["" "Standard SMT resistor, capacitor etc" "R2" "1206" 15000 23000 -3150 -3150 0 100 ""]
(
	Pad[-5905 -1181 -5905 1181 5118 2000 5718 "1" "1" "square"]
	Pad[5905 -1181 5905 1181 5118 2000 5718 "2" "2" "square"]
	ElementLine [-2362 3740 2362 3740 800]
	ElementLine [-2362 -3740 2362 -3740 800]

	)
Layer(1 "component")
(
	Line[20905 10181 20733 10181 3000 2000 "clearline"]
	Line[20733 10181 9095 21819 3000 2000 "clearline"]
)
Layer(2 "solder")
(
)
Layer(3 "GND")
(
)
Layer(4 "power")
(
)
Layer(5 "signal1")
(
)
Layer(6 "signal2")
(
)
Layer(7 "unused")
(
)
Layer(8 "unused")
(
)
Layer(9 "silk")
(
)
Layer(10 "silk")
(
)
NetList()
(
	Net("ratDrawn1" "(unknown)")
	(
		Connect("R1-2")
		Connect("R2-1")
	)
)

Attachment: tc.tgz.sig
Description: Binary data

Attachment: wontbreak.pcb.sig
Description: Binary data


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