On Wed, 2011-05-11 at 19:05 +0100, Thomas Oldbury wrote: > Sometimes, I want to add an inner polygon area to a plane in PCB. The > area might be a power supply which only has to cover a small area; e.g. > 1.8V in a predominantly 3.3V area. However, if I just draw a polygon on > top of the plane, there is no cut-out formed and I get shorts. To do > what I want, I must cut a hole in the main polygon plane, then add my > smaller polygon into it. This is very time consuming and changing the > plane once created is very difficult. Is there a way to get PCB to > support nested polygons? Not easily. For many power plane cases, these polygons won't actually be truly nested, so it is impossible to infer which polygon the user wishes to clip the other. Perhaps it would be possible to support a flag on the "smaller", clippiING polygon which makes it "bully" other polygons away from it, but again - it is not clear what to do in the case where two polygons with this flag touch each other. (Just short with each other I guess). This class of object would not be so much a "pour", but behave more like a line or arc segment. I'm guessing we would still need to retain support for clipping it against pins, pads, lines and arcs. Shouldn't take "that" much code to make it happen (I already implemented a similar feature once before), I just need to hear that there is general consensus that it is a sensible thing to do. Often for the kind of inner layers you describe, you want some complex boolean logic operation to produce the final shape from various sources. Packages like Altium (which springs to mind), let you define a layer in terms of its _negative_, so you split up a power plane by defining the _boundary_ between the two (or more) regions. Perhaps the way is to go more like mech-CAD systems in defining geometry based upon a hierarchy of boolean operations. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)
Attachment:
signature.asc
Description: This is a digitally signed message part
_______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user