gEDA-user: Support for busses

[Bill Cox <bill@viasic.com>]

Hi.

To complete the IC I'm designing using gschem for schematics, I need bus 
support.  It looks like busses are there in the schematics, and I can 
enhance the gdatabase engine to do what I need.

I'm sure there's already been some discussion on this, but I need to go 
implement it now.  What seems good to me is:

-- Busses get netname attributes of the form "FOO[3:0],BAR[2],ENWR". 
Net's tapping busses is for visual apperance.  The connection to the 
bus is implicit in the signal name that must appear on the net somewhere 
anyway.  Multiple signals can be in a bus by separating the signal names 
with commas.
-- I/O flags get simpler names that can take a range like "FOO[3:0]", 
but the comma thing is not allowed.
-- Instance names can be like "REG[0]" or even "REG[3][4]", but this 
will have no effect.  Names like "REG[7:0]" would be illegal until we 
add support for instance arrays.

What do you think?

I've attached a test schematic, and all the symbols it uses.  It also 
shows how I currently deal with hierarchy.

Bill

v 20030901
U 36400 50000 38400 50000 10 0
{
T 37000 50000 5 10 1 1 0 0
netname=IN[0:3]
}
C 39000 51000 1 0 0 inv.sym
{
T 39500 51300 5 10 1 1 0 2
refdes=IBUF[0]
T 39700 51765 5 6 1 0 0 0
P=2u
T 39700 51665 5 6 1 0 0 0
N=1u
}
C 39000 50000 1 0 0 inv.sym
{
T 39500 50300 5 10 1 1 0 2
refdes=IBUF[1]
T 39700 50765 5 6 1 0 0 0
P=2u
T 39700 50665 5 6 1 0 0 0
N=1u
}
C 39000 49000 1 0 0 inv.sym
{
T 39500 49300 5 10 1 1 0 2
refdes=IBUF[2]
T 39700 49765 5 6 1 0 0 0
P=2u
T 39700 49665 5 6 1 0 0 0
N=1u
}
C 39000 48000 1 0 0 inv.sym
{
T 39500 48300 5 10 1 1 0 2
refdes=IBUF[3]
T 39700 48765 5 6 1 0 0 0
P=2u
T 39700 48665 5 6 1 0 0 0
N=1u
}
U 38400 51500 38400 48500 10 1
N 38400 48500 39000 48500 4
{
T 38500 48500 5 10 1 1 0 0
netname=IN[3]
}
N 38400 49500 39000 49500 4
{
T 38500 49500 5 10 1 1 0 0
netname=IN[2]
}
N 38400 50500 39000 50500 4
{
T 38500 50500 5 10 1 1 0 0
netname=IN[1]
}
N 39000 51500 38400 51500 4
{
T 38500 51500 5 10 1 1 0 0
netname=IN[0]
}
U 40700 51500 40700 48500 10 1
N 40700 48500 40100 48500 4
{
T 40000 48500 5 10 1 1 0 0
netname=OUT[3]
}
N 40700 49500 40100 49500 4
{
T 40000 49500 5 10 1 1 0 0
netname=OUT[2]
}
N 40700 50500 40100 50500 4
{
T 40000 50500 5 10 1 1 0 0
netname=OUT[1]
}
N 40100 51500 40700 51500 4
{
T 40000 51500 5 10 1 1 0 0
netname=OUT[0]
}
U 40700 50000 42700 50000 10 0
{
T 41500 50000 5 10 1 1 0 0
netname=OUT[3:0]
}
C 35600 49900 1 0 0 in.sym
{
T 35600 50000 5 10 1 1 0 7
value=IN[3:0]
}
C 42700 49900 1 0 0 out.sym
{
T 43500 50000 5 10 1 1 0 1
value=OUT[3:0]
}
v 20030901
P 600 100 800 100 1 0 1
{
T 650 150 5 6 0 1 0 0
pinnumber=Z
T 650 150 5 6 0 1 0 0
pinlabel=Z
T 650 150 5 6 0 0 0 0
pintype=in
T 650 150 5 6 0 0 0 0
pinseq=1
}
L 600 100 500 200 6 0 0 0 -1 -1
L 600 100 500 0 6 0 0 0 -1 -1
T 0 100 8 10 1 1 0 7
value=pinlabel
T 0 0 8 10 0 1 0 0
device=FLAG
L 500 200 100 200 3 0 0 0 -1 -1
L 100 200 100 0 3 0 0 0 -1 -1
L 100 0 500 0 3 0 0 0 -1 -1
v 20030901
L 300 800 800 500 3 0 0 0 -1 -1
L 800 500 300 200 3 0 0 0 -1 -1
L 300 800 300 500 3 0 0 0 -1 -1
L 300 500 300 200 3 0 0 0 -1 -1
V 850 500 50 6 0 0 0 -1 -1 0 0 -1 -1 -1 -1
P 1100 500 900 500 1 0 0
{
T 915 550 5 8 0 1 0 0
pinnumber=Z
T 915 550 5 8 0 0 0 0
pinlabel=Z
T 915 550 5 8 0 0 0 0
pintype=out
T 915 550 5 8 0 0 0 0
pinseq=1
}
P 300 500 0 500 1 0 1
{
T 100 550 5 8 0 1 0 0
pinnumber=D
T 100 550 5 8 0 1 0 0
pinlabel=D
T 100 550 5 8 0 1 0 0
pintype=in
T 100 550 5 8 0 0 0 0
pinseq=2
}
T 500 300 5 10 1 1 0 2
refdes=U?
T 700 765 8 6 1 0 0 0
P=2u
T 700 665 8 6 1 0 0 0
N=1u
T 0 165 8 10 0 1 0 0
source=inv.sch
v 20030901
N 51400 57600 51400 56800 4
N 51400 57200 52000 57200 4
N 50800 56400 50800 58000 4
N 50800 57200 50200 57200 4
N 51400 58400 51400 58800 4
N 51400 56000 51400 55600 4
C 49400 57100 1 0 0 in.sym
{
T 49400 57100 5 10 1 1 0 6
value=D
}
C 52000 57100 1 0 0 out.sym
{
T 52800 57100 5 10 1 1 0 0
value=Z
}
C 50800 56000 1 0 0 nmos.sym
{
T 51600 56600 5 10 1 1 0 0
refdes=M1
T 51600 56200 5 6 1 0 0 0
w={N}
}
C 50800 57600 1 0 0 pmos.sym
{
T 51600 58200 5 10 1 1 0 0
refdes=M2
T 51600 57800 5 6 1 0 0 0
w={P}
}
C 51200 58800 1 0 0 vdd.sym
C 51200 55200 1 0 0 vss.sym
v 20030901
P 0 100 200 100 1 0 0
{
T 150 150 5 6 0 1 0 0
pinnumber=D
T 150 150 5 6 0 1 0 0
pinlabel=D
T 150 150 5 6 0 0 0 0
pinseq=1
T 0 100 5 10 0 1 0 0
pintype=out
}
L 700 100 600 200 6 0 0 0 -1 -1
L 700 100 600 0 6 0 0 0 -1 -1
T 800 100 8 10 1 1 0 1
value=pinlabel
T 0 0 8 10 0 1 0 0
device=FLAG
L 600 200 200 200 3 0 0 0 -1 -1
L 200 0 200 200 3 0 0 0 -1 -1
L 200 0 600 0 3 0 0 0 -1 -1
v 20030901
L 400 600 400 200 3 0 0 0 -1 -1
T 600 500 5 10 0 0 0 0
device=NMOS_TRANSISTOR
L 300 600 300 200 3 0 0 0 -1 -1
L 400 600 600 600 3 0 0 0 -1 -1
L 400 200 600 200 3 0 0 0 -1 -1
P 0 400 300 400 1 0 0
{
T 0 500 5 10 0 1 0 0
pinnumber=G
T 0 500 5 10 0 1 0 0
pinlabel=G
T 0 500 5 10 0 0 0 0
pinseq=2
T 0 400 5 10 0 1 0 0
pintype=in
}
P 600 600 600 800 1 0 1
{
T 400 700 5 10 0 1 0 0
pinnumber=D
T 400 700 5 10 0 1 0 0
pinlabel=D
T 400 700 5 10 0 0 0 0
pinseq=1
T 600 600 5 10 0 1 0 0
pintype=io
}
P 600 200 600 0 1 0 1
{
T 400 0 5 10 0 1 0 0
pinnumber=S
T 400 0 5 10 0 1 0 0
pinlabel=S
T 400 0 5 10 0 0 0 0
pinseq=3
T 600 200 5 10 0 1 0 0
pintype=io
}
T 800 600 8 10 1 1 0 0
refdes=M?
T 800 200 9 6 1 0 0 0
w=1u
T 800 300 9 6 0 0 0 0
l=.35u
T 0 0 8 10 0 1 0 0
description=Basic N-MOS transistor
T 0 0 8 10 0 1 0 0
model=MODN
T 0 0 8 10 0 1 0 0
net=vss:B
v 20030901
L 400 600 400 200 3 0 0 0 -1 -1
T 600 200 5 10 0 0 0 0
device=PMOS_TRANSISTOR
L 300 600 300 200 3 0 0 0 -1 -1
L 400 600 600 600 3 0 0 0 -1 -1
L 400 200 600 200 3 0 0 0 -1 -1
P 600 600 600 800 1 0 1
{
T 400 700 5 10 0 1 0 0
pinnumber=D
T 400 700 5 10 0 1 0 0
pinlabel=D
T 400 700 5 10 0 0 0 0
pinseq=1
T 600 600 5 10 0 1 0 0
pintype=io
}
P 600 200 600 0 1 0 1
{
T 400 0 5 10 0 1 0 0
pinnumber=S
T 400 0 5 10 0 1 0 0
pinlabel=S
T 400 0 5 10 0 0 0 0
pinseq=3
T 600 200 5 10 0 1 0 0
pintype=io
}
P 200 400 0 400 1 0 1
{
T 0 500 5 10 0 1 0 0
pinnumber=G
T 0 500 5 10 0 1 0 0
pinlabel=G
T 0 500 5 10 0 0 0 0
pinseq=2
T 100 400 5 10 0 1 0 0
pintype=in
}
T 800 600 8 10 1 1 0 0
refdes=M?
T 800 200 9 6 1 0 0 0
w=1u
T 800 300 9 6 0 0 0 0
l=.35u
V 250 400 51 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 0 0 8 10 0 1 0 0
model=MODP
T 0 0 8 10 0 1 0 0
net=vdd:B