RE: gEDA-user: Support for busses

["Keith Outwater" <Keith_Outwater@microvision.com>]

> -----Original Message-----
> From: Bill Cox [mailto:bill@viasic.com]
> Sent: Wednesday, November 05, 2003 7:14 AM
> To: geda-user@seul.org
> Subject: gEDA-user: Support for busses
> 
> 
> Hi.
> 
> To complete the IC I'm designing using gschem for schematics, 
> I need bus 
> support.  It looks like busses are there in the schematics, and I can 
> enhance the gdatabase engine to do what I need.
> 
> I'm sure there's already been some discussion on this, but I 
> need to go 
> implement it now.  What seems good to me is:
> 
> -- Busses get netname attributes of the form "FOO[3:0],BAR[2],ENWR". 
>  Net's tapping busses is for visual apperance.  The connection to the 
> bus is implicit in the signal name that must appear on the 
> net somewhere 
> anyway. 

Yes, but what if you don't name the net?  Wouldn't it be nice if you could simply rip off a bus member using a 'rule' attribute and forget about having to name the ripped net?
Here's an example of why this is a Good Thing:
Let's say I create a schematic with four memory chips which connect to a 32 bit data bus named cpu_data[31:0].  On each chip, I rip 8 bits from the bus.  Most schematic editors require me to name each ripped net: cpu_data[0], cpu_data[1], ...  Now this is a big hassle and does not add any useful information whatsoever to the schematic since I already know the bus name (it's cpu_data).  What happens now when I decide to change the bus name to local_data[31:0]?  You guessed it: everything has to be renamed.  This makes editing a pain and reuse a real pain.

Instead of this drudgery, how about allowing a 'rule' attribute to be placed on a bus ripper to indicate the index of the bus member to be connected to the ripped net?  For example, if I want to rip cpu_data[4] off of the bus, I place a bus ripper on the bus and change the rule attribute to 4.  Whatever net I connect to the other end of the bus ripper gets connected to cpu_data[4].  Simple.  This approach completely avoids the redundant placement of bus names on the ripped nets and allows the entire bus to be renamed by changing the bus name in one place.  Obviously, there needs to be a net name resolution policy, but that's no big deal.  Better yet, if there is a net name conflict, pop up a dialog and ask the user what he wants to do.

BTW, as far as I know, only Mentor's Design Architect gets this stuff right.  Maybe Cadence does too.  Then again both tools cost some real money.

>Multiple signals can be in a bus by separating the 
> signal names 
> with commas.
> -- I/O flags get simpler names that can take a range like "FOO[3:0]", 
> but the comma thing is not allowed.
> -- Instance names can be like "REG[0]" or even "REG[3][4]", but this 
> will have no effect.  Names like "REG[7:0]" would be illegal until we 
> add support for instance arrays.
> 
> What do you think?
> 
> I've attached a test schematic, and all the symbols it uses.  It also 
> shows how I currently deal with hierarchy.
> 
> Bill