RE: gEDA-user: VHDL Compiler

["EATON,JOHN (HP-Vancouver,ex1)" <john.eaton@hp.com>]

Take any VHDL program. Strip out the 2/3's of the listing that
provides no useful information and you will have a good idea
of what the verilog would look like.

Anytime a textbook gives both verilog and VHDL for a circuit
the VHDL is usually 3 times as large as the verilog. Compiler
writers love it because it explictly spells out everything.
Mangers love it because it forces designers to fully define
everything up front. Engineers hate it because it gives us
carple_tunnnel.

John Eaton


  

-----Original Message-----
From: owner-geda-user@seul.org [mailto:owner-geda-user@seul.org]On
Behalf Of Eric N.
Sent: Monday, November 10, 2003 9:20 AM
To: geda newsgroup
Subject: Re: gEDA-user: VHDL Compiler


Where can I see a sample of Verilog code.  In simple terms and short how
do the two differ?  I read some V vs V messages a few secs ago but
without knowing Verilog it's hard to agree with one or the other.

Eric


> 
> If you can switch to Verilog, then Icarus Verilog rocks -- I've used
> it to do a couple of small-to-mid sized projects.
> 
> As for a waveform viewer, GTKWave is the tool of choice, IMHO:
> 
> http://www.cs.man.ac.uk/apt/tools/gtkwave/
> 
> Stuart
> 
> 
> > 
> > Can someone recommend a open source VHDL compiler that they like using. 
> > I have to simulate a control unit on a processor and I also need a way
> > to print out the output of the different timing signals. I currently use
> > vsim (mentor graphics) on the school server but I will be traveling over
> > the holiday and without a network connection plus you can only spend so
> > much time with your family.  
> > 
> > Thank you. 
> > 
> > -- 
> > Eric N. <enist@cox.net>
> > 
> > 
-- 
Eric N. <enist@cox.net>