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Re: gEDA-user: VHDL Compiler
John Sheahan wrote:
in Europe,
VHDL is the FPGA language of choice. In the US, it's about
half-and-half. In Japan, they prefer Verilog. Apparently, in Japan
they prefer to keep using what has worked well in the past.
I've worked with counterexamples to all of these - not that I'd dispute
the general thrust much. For asic I would have guessed the USA leaned
to verilog a tad. And Australia is VHDL. (all .001% of the world market)..
Perhaps the key - as you observe - is to emphasize translator tools
to reduce the wastage wherever possible?
Unfortunately some things are hard to translate, although less so with
the arrival of Verilog 2000, and less so for synthesisable code. Off the
top of my head (I'm sure there are better examples) bidirectional
transmission gates, the Verilog conditional operator where the result of
the expression is 'x', 4-value logic vs. n-value logic, the general
issue of VHDL's more sophisticated type system (enumerations,
multi-dimensional arrays, records, etc).
Anyway, what does it really matter if we have two languages? Sometime
soon we'll have a choice of a lot more - SystemVerilog, SystemC, 'e'
when it becomes synthesisable, Handel-C if it ever takes off, and so on.
There's no point reducing everything to the lowest common denominator.
Imagine telling a programmer that they weren't allowed to write in C,
C++, Java, ML, and a million other languages just because someone had
already written Fortran. IMO, the more the merrier - it shows that the
HW world is finally starting to take language design seriously, albeit
20 years too late.
Evan