John Sheahan wrote:
Synopsys started life with DC, around 1988. Back then, the tool flow was Verilog-XL (Gateway, Cadence) for simulation, DC for synthesis. Synopsys didn't need a simulator. They did move into VHDL, both for simulation and synthesis. However, I think it's always been clear that they would much rather that there was no VHDL, but it's taken Aart de Geus until this year to actually say it publicly.On Tue, 2003-11-11 at 21:35, Evan Lavelle wrote:5 Synopsys built their business on DC and Verilog. Synopsys have always, and are still, going to great lengths to bury VHDL.
but synopsys sold VSS as their main simulator until they bought vcs.
NC-Sim is Cadence. ModelSim is Mentor, but Mentor is a distant number 3 in EDA, with about half of Synopsys' revenues. The OP was asking about Verilog vs. VHDL, and I was pointing out that the opinions on this question were generally formed not by engineers, but by the people who own the EDA industry: ie. basically Cadence and Synopsys. One thing that strikes me is that engineers are very quick to complain when Microsoft tries to form public opinion, but generally don't even notice when the same thing happens in the EDA industry.6 Cadence and Synopsys basically own EDA.ncsim? modelsim? is EDA or simulation the question here?
perhaps it would be worth noting the speed benefits of gate level verilog here if you want to be historical too.I didn't make any technical comments on the relative merits of VHDL and Verilog. It's certainly true that Verilog has simpler types and a simpler scheduler, and that gate-level sims are consequently faster. And, if you're comparing schedulers, you could also take into account that IEEE-compliant Verilog simulators can find it difficult to simulate with the same results as XL. However, the OP wasn't doing gate-level modelling, and this is only one factor out of maybe 20 or 30 that you would have to evaluate if you were seriously comparing VHDL and Verilog.