Re: gEDA-user: VHDL Compiler

[Evan Lavelle <anti.spam1@dsl.pipex.com>]

Eric N. wrote:
> Can someone recommend a open source VHDL compiler that they like using. 
> I have to simulate a control unit on a processor and I also need a way
> to print out the output of the different timing signals. I currently use
> vsim (mentor graphics) on the school server but I will be traveling over
> the holiday and without a network connection plus you can only spend so
> much time with your family.
The simple answer to your question is to download the free Xilinx tools. 
 Unless they've changed over the last couple of years, you'll get a 
free restricted version of ModelSim (everyone calls it ModelSim, rather 
than vsim), which should be more than enough for a school project. Ask 
on comp.arch.fpga if you need more details on exactly what the 
restricted version does; my recollection is that it does pretty much 
everything.

And, if you're going to ask VHDL vs. Verilog questions, here are a few 
things you need to remember:

1  A tiny proportion of engineers write both VHDL and Verilog, and you 
need to ignore almost everything you're told;

2  The vast majority of engineers write the language that their employer 
tells them to write, not the language that may or may not be the best 
for the job;

3  Opinions on this subject are driven almost exclusively by the 
vendors, not the users, most of whom have neither the time nor the 
inclination to learn and evaluate multiple languages. Consider these 
simple facts:

4  Cadence owned Verilog until 1995. They were forced to make it public 
domain only because VHDL had already been an IEEE standard since 1987. 
Cadence went to great lengths to bury VHDL.

5  Synopsys built their business on DC and Verilog. Synopsys have 
always, and are still, going to great lengths to bury VHDL.

6  Cadence and Synopsys basically own EDA.

Go figure..

Evan Lavelle