Re: gEDA-user: VHDL Compiler

[Evan Lavelle <anti.spam1@dsl.pipex.com>]

Bill Cox wrote:

> I also know of simple things that require context to parse, even 
> component declarations.  In VHDL, basically you're forced into building 
> a tree-based parse tree, so you can figure out what's going on from the 
> context.  Verilog, in contrast (at least the structural part), can be 
> directly parsed into a language database, skipping the generic 
> parse-tree step.  This dramatically simplifies the code, and speeds up 
> parsing.  VHDL will never parse as fast as Verilog.
>
> Of all the programmers I know who wrote both Verilog and VHDL parsers, 
> all prefer to parse Verilog.  I'm not making this up.  Go ask respected 
> guys in the field, like Ken McLevain at Synplicity.
I certainly agree with you that it's a (very) difficult job to write a 
VHDL compiler; it was pretty brave to take on VHDL with Lex and Yacc. 
It's possible but, as you point out, you need context sensitivity. Most 
people seem to hand-code a lexer, or go with an LL or GLR generator 
(SAVANT, for example, uses ANTLR/PCCTS, which is LL-based; anyone who 
wants to write 'free' VHDL tools could do a lot worse than using SAVANT 
as a starting point).

> BTW, I'm still interested in C-like HDLs.  If you have a good start on 
> one, I'd be interested in checking it out.
I'm afraid mine's commercial. The two open source ones I know about are 
SpecC <http://www.ics.uci.edu/~specc/>, which I haven't used, and 
SystemC. I've occasionally thought that it would be worthwhile to write 
a preprocessor for SystemC to make it more usable as an HDL. SystemPerl 
(<http://www.veripool.com/systemperl.html>) does some preprocessing, but 
what's really needed is something that turns simple VHDL- or 
Verilog-like module instantiations, concurrent signal assignments, and 
so on, into the fairly complex C++ that SystemC needs. Now, that would 
be worth paying real money for..

Evan