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Re: gEDA-user: VHDL Compiler
I gree. In general both Verilog and VHDL are nearly equivalent from the
end-user perspective.
However, from a developer standpoint, Verilog is far superior. VHDL has
all kinds of crazy nonsense that almost no one ever uses. Also, the
VHDL LRM (language reference manual) is a worthless pile, generally a
waste of paper. It was designed by commitee, and never tested. Anyone
claiming to be VHDL compliant is not telling you the whole truth: There
is no such thing as standard VHDL, so how can you be compliant? The LRM
is so full of bugs, that the implementer spends half his time making up
work-arounds for holes in the spec. A simple datapoint: My structural
Verilog reader is 5183 lines of hand written C code. My structural VHDL
reader is 9744.
Part of the strong Verilog bias you'll find out there comes from the
tool developer community. It's no accident that Icarus Verilog is ahead
of GHDL. Given limited resources in the open-source community, I think
a focus on Verilog makes a lot of sense.
Bill
Stuart Brorson wrote:
For Verilog code samples, try downloading some of the cores off of
OpenCores.org.
In short and simple terms, they differ syntatically, but serve
basically the same design niche. VHDL is more structured, organized,
& wordy, Verilog is more cryptic and less structured (but not too much
so). In a sense, VHDL is more like Pascal, Verilog is more like C.
Note that both Pascal & C (like VHDL and Verilog) serve the same
design purpose.
Some would say that VHDL is slightly "higher level" than Verilog, and
that Verilog is slightly "closer to gates" than VHDL. As a practical
matter, these distinctions are not relevant to the ordinary designer.
You won't notice a bit of difference w.r.t. the power of the language
in your project.
For more info, I suggest Googling up the comp.lang.vhdl or
comp.lang.verilog FAQs.
Stuart
Where can I see a sample of Verilog code. In simple terms and short how
do the two differ? I read some V vs V messages a few secs ago but
without knowing Verilog it's hard to agree with one or the other.
Eric
If you can switch to Verilog, then Icarus Verilog rocks -- I've used
it to do a couple of small-to-mid sized projects.
As for a waveform viewer, GTKWave is the tool of choice, IMHO:
http://www.cs.man.ac.uk/apt/tools/gtkwave/
Stuart
Can someone recommend a open source VHDL compiler that they like using.
I have to simulate a control unit on a processor and I also need a way
to print out the output of the different timing signals. I currently use
vsim (mentor graphics) on the school server but I will be traveling over
the holiday and without a network connection plus you can only spend so
much time with your family.
Thank you.
--
Eric N. <enist@cox.net>
--
Eric N. <enist@cox.net>