Re: gEDA-user: VHDL Compiler

[Stephen Williams <steve@icarus.com>]

Bill Cox wrote:
> I gree.  In general both Verilog and VHDL are nearly equivalent from the 
> end-user perspective.
>
> However, from a developer standpoint, Verilog is far superior.  VHDL has 
> all kinds of crazy nonsense that almost no one ever uses.  Also, the 
> VHDL LRM (language reference manual) is a worthless pile, generally a 
> waste of paper.  It was designed by commitee, and never tested.  Anyone 
> claiming to be VHDL compliant is not telling you the whole truth:  There 
> is no such thing as standard VHDL, so how can you be compliant?  The LRM 
> is so full of bugs, that the implementer spends half his time making up 
> work-arounds for holes in the spec.  A simple datapoint:  My structural 
> Verilog reader is 5183 lines of hand written C code.  My structural VHDL 
> reader is 9744.
Personally, I would not choose to be so vociferous in an attack
of VHDL. VHDL advocates would point to that the standard is clear
on many things that Verilog is vague about. This is especially
true of simulation scheduling.

My biases are well known, but *both* LRMs are freaky and buggy
so I'm not going to complain about VHDL while I'm busy fixing
Verilog.

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."