Re: gEDA-user: VHDL Compiler

[Evan Lavelle <anti.spam1@dsl.pipex.com>]

Bill Cox wrote:
> I gree.  In general both Verilog and VHDL are nearly equivalent from the 
> end-user perspective.
>
> However, from a developer standpoint, Verilog is far superior.  VHDL has 
> all kinds of crazy nonsense that almost no one ever uses.  Also, the 
> VHDL LRM (language reference manual) is a worthless pile, generally a 
> waste of paper.  It was designed by commitee, and never tested.  Anyone 
> claiming to be VHDL compliant is not telling you the whole truth:  There 
> is no such thing as standard VHDL, so how can you be compliant?  The LRM 
> is so full of bugs, that the implementer spends half his time making up 
> work-arounds for holes in the spec.  A simple datapoint:  My structural 
> Verilog reader is 5183 lines of hand written C code.  My structural VHDL 
> reader is 9744.
>
> Part of the strong Verilog bias you'll find out there comes from the 
> tool developer community.  It's no accident that Icarus Verilog is ahead 
> of GHDL.  Given limited resources in the open-source community, I think 
> a focus on Verilog makes a lot of sense.
I wouldn't normally reply to this sort of nonsense, but a number of 
people seem to be reading it, and they deserve better. BTW, I've read 
both the VHDL and the Verilog LRMs, as well as several other books on 
both languages, and I've used both. I've also written a C-like HDL.

The VHDL LRM is *exceptionally* well written. It is detailed and 
precise, and leaves almost no room for confusion. This has always been 
the case. There was a maintenance revision in 2001, and the fixes were 
trivial. Yes, it can be difficult to read, but it's a reference manual, 
designed for those who implement the language, and it does an excellent 
job at it. It's not intended for someone who's new to the language. 
There *is* an absolutely standard VHDL, and there always has been, with 
the proviso that the '93 revision made some changes over the '87 
revision, and the '87 revision contained a few ambiguities. There are 
virtually *no* bugs in the LRM, and implementors absolutely do *not* 
have to 'make up work-arounds for holes in the spec.'. Somer vendors 
conform to the LRM better than other vendors, but that's a different matter.

The Verilog LRM is not, by any stretch of the imagination, in the same 
league. You only have to read and compare a small part of each LRM to 
see this. Some of the reason for this is historical; there was a long 
time when Verilog-XL was effectively the reference point for the 
language, and it took a long time to recover from this. VHDL was derived 
from Ada, which made it easier to document; Verilog was new, and was 
poorly defined from the start.

There are several other free VHDL simulators; just check the VHDL FAQ. 
Icarus is probably ahead of all of them - I haven't looked for a couple 
of years - and the reason is simple: Steve Williams has put in the time 
and has done a good job. It's got nothing to do with the language, per se.

As for "VHDL has all kinds of crazy nonsense that almost no one ever 
uses", do you think that perhaps the people who defined Verilog 2000 
might disagree with you?

Evan Lavelle