Re: gEDA-user: VHDL Compiler

[Bill Cox <bill@viasic.com>]

Evan Lavelle wrote:

> Bill Cox wrote:
>
> > I gree.  In general both Verilog and VHDL are nearly equivalent from 
> > the end-user perspective.
> >
> > However, from a developer standpoint, Verilog is far superior...
> I wouldn't normally reply to this sort of nonsense, but a number of 
> people seem to be reading it, and they deserve better. BTW, I've read 
> both the VHDL and the Verilog LRMs, as well as several other books on 
> both languages, and I've used both. I've also written a C-like HDL.
I can see that it was a mistake, as Stevphen Williams pointed out, to 
flame VHDL so hard.  However, I've implemented both Verilog and VHDL 
structural parsers.  The Verilog LRM wasn't really needed much during 
this process.  I was able to write the parser mostly from example code. 
The VHDL parser was a different story.  I haven't seen a VHDL LRM since 
the '93 version, so I can't speak about the 2001 version.  However, the 
'93 version was bad in it's accuracy, although I agree it was well 
written.  It was clearly never tested.

Here's some comments that still exist in my yacc VHDL parser:

/*--------------------------------------------------------------------------------------------------
 The language reference is in error when it says to use selectedNames.
 The prefix must be a simple prefix.
--------------------------------------------------------------------------------------------------*/
useClause: KWUSE simpleSelectedNameList ';'

/*--------------------------------------------------------------------------------------------------
 Again, the language manual erroneously specifies name, not simpleName.
--------------------------------------------------------------------------------------------------*/
architectureBody: KWARCHITECTURE IDENTIFIER KWOF simpleName KWIS

/*--------------------------------------------------------------------------------------------------
 VHDL is really SCREWED up here.  Association elements are not LAR1
 parseable.  The optional formal can look just like the required actual 
part.
--------------------------------------------------------------------------------------------------*/
associationElement: formalOrActualPart KWRIGHT_ARROW formalOrActualPart

I also know of simple things that require context to parse, even 
component declarations.  In VHDL, basically you're forced into building 
a tree-based parse tree, so you can figure out what's going on from the 
context.  Verilog, in contrast (at least the structural part), can be 
directly parsed into a language database, skipping the generic 
parse-tree step.  This dramatically simplifies the code, and speeds up 
parsing.  VHDL will never parse as fast as Verilog.

Of all the programmers I know who wrote both Verilog and VHDL parsers, 
all prefer to parse Verilog.  I'm not making this up.  Go ask respected 
guys in the field, like Ken McLevain at Synplicity.

BTW, I'm still interested in C-like HDLs.  If you have a good start on 
one, I'd be interested in checking it out.

Bill