Re: gEDA-user: VHDL Compiler

[Alex Perry <alex.perry@qm.com>]

Evan Lavelle wrote:
> The VHDL LRM is *exceptionally* well written.   [...]
> The Verilog LRM is not, by any stretch of the imagination, in the same
> league.

Fine.  My point was that the quality of the language is lost in the
synthesizers, so if your goal is to end up with a solid logic design
then VHDL no longer has any usage benefits over Verilog.  As an end
user,
I care about the status of available implementations ... not of the
LRMs.

> There are several other free VHDL simulators; just check the VHDL FAQ.
> Icarus is probably ahead of all of them - I haven't looked for a couple
> of years - and the reason is simple: Steve Williams has put in the time
> and has done a good job. It's got nothing to do with the language, per se.

For simulation, the more tightly defined language should give VHDL an
edge.
I've not got enough experience to have an opinion either way in general.

> As for "VHDL has all kinds of crazy nonsense that almost no one ever
> uses", do you think that perhaps the people who defined Verilog 2000
> might disagree with you?

Again, you have to distinguish between simulation-only and synthesizable
code.

Finally, an engineer needs to evaluate the performance of the actual
tools,
the simulator and the synthesizer, that support the planned logic
family.
That is irrespective of whether the target will be ASIC, FPGA or CPLD.
If one of the languages is better supported for the planned target, then
you are going to have to use that language irrespective of your
preferences.
In most practical senses, therefore, the whole discussion is irrelevant.