Re: gEDA-user: VHDL Compiler

[Alex Perry <alex.perry@qm.com>]

"Eric N." wrote:
> My prof. said this and I'm curious about the answers.
> Does verilog have testbenches?

Sure.  That's what I normally work with, since I tend to
write-and-regress.

> I don't know about verilog, but VHDL allows for a top down design
> from a single entity declaration through multiple layers of structural
> architectures.  At all of these levels, the system is simulatable and
> verifiable.

Given that Verilog is the main language for writing large ASICs,
I think it is safe to provide an unqualified "yes" as the answer.

> For a system which is hardware only, perhaps verilog is
> ok.  For one which includes hardware/software tradeoffs, VHDL supports
> this (I don't know if verilog does).

One of the things I like about Icarus is that I can attach a
piece of verilog (simulating a hardware device) as though it is
a subroutine library and pretend it is the real hardware.
Greatly simplifies the debugging of the new drivers under Linux.

I have yet to find someone offering that for VHDL.