Re: gEDA-user: VHDL Compiler

[sdb@cloud9.net (Stuart Brorson)]

> 
> My prof. said this and I'm curious about the answers.
> 
> Does verilog have testbenches?

A testbench is a blob of HDL code which you use to exercise your
design.  You write it yourself.  For example, if your design is a PCI
bus interface, then a testbench is a blob of code which generates PCI
bus requests & transactions.  You would hook it up to your design and
look at the response of your code to the stimulus provided  by the PCI
bus transactor.  You can write testbenches in both VHDL and Verilog. 

Oftentimes, a testbench just reads a bunch of test vectors
(e.g. signal values and times when they change) from a file
& fires them at your design.  You check the correctness of your design
by watching the response of your code using a waveform viewer.  Both
Verilog and VHDL support file IO for this purpose. 

> I don't know about verilog, but VHDL allows for a top down design
> from a single entity declaration through multiple layers of structural
> architectures.  

My first reaction would be to say: "Please speak English, not marketing
gobbledygook!"  If your professor speaks like this, it is a sign that
he doesn't actually do any real work.  

Translated into English, I think
that he is trying to say "VHDL allows you to do hierarchical designs,
i.e. you can put a lower level function inside a higher level block.
For example, you can write a 16 bit register as a module, and then
instantiate it multiple times inside a bus interface module.  Then you
can stick the bus interface module inside a larger design which
incorporates other blobs of logic, like a protocol engine.

He is (perhaps) also trying to say that you can write several types of
HDL code:  RTL, which is basically specifying the design at the gate
or register level, and "behavioral", which means that you can use
constructs like for-next loops & non-physical delays to implement
various functions.  Both Verilog & VHDL support several types of logic
design.  

So, to answer your question:  Yes, you can do this also in Verilog.

> At all of these levels, the system is simulatable and
> verifiable.  

True for both.

> For a system which is hardware only, perhaps verilog is
> ok.  For one which includes hardware/software tradeoffs, VHDL supports
> this (I don't know if verilog does).

Despite what your prof says, neither VHDL nor Verilog really support
HW/SW co-design very well, although you can do it in both.  However,
doing a HW/SW co-design is a real PITA & is a major project.  At one
of my former places of employment we had a huge team of experienced
guys dedicated to doing just that for a chip design.  Does your prof
really want you to do this?   Does he have any idea of the difficulty
involved?  

Doing HW/SW co-design is a topic of current research/development
interest.  Check out SystemVerilog, Handel-C, or SystemC (no catcalls,
please) if this is your goal.  

Stuart

> 
> 
> 
> On Mon, 2003-11-10 at 14:07, Bill Cox wrote:
> > I gree.  In general both Verilog and VHDL are nearly equivalent from the 
> > end-user perspective.
> > 
> > However, from a developer standpoint, Verilog is far superior.  VHDL has 
> > all kinds of crazy nonsense that almost no one ever uses.  Also, the 
> > VHDL LRM (language reference manual) is a worthless pile, generally a 
> > waste of paper.  It was designed by commitee, and never tested.  Anyone 
> > claiming to be VHDL compliant is not telling you the whole truth:  There 
> > is no such thing as standard VHDL, so how can you be compliant?  The LRM 
> > is so full of bugs, that the implementer spends half his time making up 
> > work-arounds for holes in the spec.  A simple datapoint:  My structural 
> > Verilog reader is 5183 lines of hand written C code.  My structural VHDL 
> > reader is 9744.
> > 
> > Part of the strong Verilog bias you'll find out there comes from the 
> > tool developer community.  It's no accident that Icarus Verilog is ahead 
> > of GHDL.  Given limited resources in the open-source community, I think 
> > a focus on Verilog makes a lot of sense.
> > 
> > Bill
> > 
> > Stuart Brorson wrote:
> > 
> > >For Verilog code samples, try downloading some of the cores off of
> > >OpenCores.org.  
> > >
> > >In short and simple terms, they differ  syntatically, but serve
> > >basically the same design niche.  VHDL is more structured, organized,
> > >& wordy, Verilog is more cryptic and less structured (but not too much
> > >so).  In a sense, VHDL is more like Pascal, Verilog is more like C.
> > >Note that both Pascal & C (like VHDL and Verilog)  serve the same
> > >design purpose. 
> > >
> > >Some would say that VHDL is slightly "higher level" than Verilog, and
> > >that Verilog is slightly "closer to gates" than VHDL.  As a practical
> > >matter, these distinctions are not relevant to the ordinary designer.
> > >You won't notice a bit of difference w.r.t. the power of the language
> > >in your project.
> > >
> > >For more info, I suggest Googling up the comp.lang.vhdl or
> > >comp.lang.verilog FAQs.
> > >
> > >Stuart
> > >
> > >  
> > >
> > >>Where can I see a sample of Verilog code.  In simple terms and short how
> > >>do the two differ?  I read some V vs V messages a few secs ago but
> > >>without knowing Verilog it's hard to agree with one or the other.
> > >>
> > >>Eric
> > >>
> > >>
> > >>    
> > >>
> > >>>If you can switch to Verilog, then Icarus Verilog rocks -- I've used
> > >>>it to do a couple of small-to-mid sized projects.
> > >>>
> > >>>As for a waveform viewer, GTKWave is the tool of choice, IMHO:
> > >>>
> > >>>http://www.cs.man.ac.uk/apt/tools/gtkwave/
> > >>>
> > >>>Stuart
> > >>>
> > >>>
> > >>>      
> > >>>
> > >>>>Can someone recommend a open source VHDL compiler that they like using. 
> > >>>>I have to simulate a control unit on a processor and I also need a way
> > >>>>to print out the output of the different timing signals. I currently use
> > >>>>vsim (mentor graphics) on the school server but I will be traveling over
> > >>>>the holiday and without a network connection plus you can only spend so
> > >>>>much time with your family.  
> > >>>>
> > >>>>Thank you. 
> > >>>>
> > >>>>-- 
> > >>>>Eric N. <enist@cox.net>
> > >>>>
> > >>>>
> > >>>>        
> > >>>>
> > >>-- 
> > >>Eric N. <enist@cox.net>
> > >>
> > >>
> > >>    
> > >>
> > >
> > >
> > >
> > >  
> > >
> -- 
> Eric N. <enist@cox.net>
> 
>