Re: gEDA-user: VHDL Compiler

[sdb@cloud9.net (Stuart Brorson)]

> 
> My goal is not cat calls but to learn!!!!

Well & good.  From my perspective, you would learn equally well from
either Verilog or VHDL.  My experience is that Verilog is more
prevalant in the commercial world in the USA, VHDL may be more
prevalant in Europe (from what I hear).  Academics are more varied,
and tend to use either VHDL or Verilog, depending upon what they have
learned.   (Since VHDL was defined by an IEEE committee made up of
academics, this may have contributed to its popularity in academia.
Of course, this may also be why real HW types hate it. . . .)

Some purists believe that VHDL is a better defined and more
structured language than Verilog; therefore, academics may like it
better.  Practical engineers like Verilog better because it gives them
more control over gates and registers (they think), and because you
don't need to type all those weenie BEGIN and END blocks & other
unnecssary & pedantic declarations.

As you see from all the posts on this topic, Verilog vs. VHDL is a
religious decision.  Realistically, either will work well for you.

As for the cat calls and brickbats, well, I was referring to SystemC,
which was developed to enable HW/SW co-design, with the goal being
that you could create a HW design, and then run C code against it.  
Hardware types usually hate SystemC with a passion because it's
basically just a bunch of class extensions to C++, and comes with all
the nasty baggage which always accompanies SW development -- obscure
bugs, unpleasant design environments (gcc + emacs), and the necessity
to learn to program in C++ well.  It doesn't help that you
still can't synthesize a design using SystemC (right?).  Software types
usually don't even know SystemC exists.  Therefore, it looks like this
particular HDL is basically stillborn & not worth learning.

This is not a good thing; several places I have worked had some
architect/genuis type who created a giant, high-level C++ model of the
system under construction as a kind of prototype.  He then would
lead/consult with the ASIC designers about how to actually implement
their portion of the design.  This approach seemed to work quite well.
Maybe HandelC or SystemVerilog will perform this role in the future.
They might be good things to learn. . . .

Stuart