Re: gEDA-user: VHDL Compiler

[John Sheahan <jrsheahan@optushome.com.au>]

> Synopsys started life with DC, around 1988. Back then, the tool flow was 
> Verilog-XL (Gateway, Cadence) for simulation, DC for synthesis. Synopsys 
> didn't need a simulator. They did move into VHDL, both for simulation 
> and synthesis. However, I think it's always been clear that they would 
> much rather that there was no VHDL, but it's taken Aart de Geus until 
> this year to actually say it publicly.
> 

possibly. I suspect there was a window there where Synopsys would have
been thrilled if VHDL and (ie VSS and the appropriate DC reader)  could 
have killed verilog championed by their main competitor at the time. 
However VSS was not competitive enough against XL.


> > 
> >>6  Cadence and Synopsys basically own EDA.
> > 
> > 
> > ncsim? modelsim?  is EDA or simulation the question here?
> 
> NC-Sim is Cadence. ModelSim is Mentor, but Mentor is a distant number 3 
> in EDA, with about half of Synopsys' revenues. 

my point here was Menotor appear dominant in mixed mode simulation, with
Cadence now starting to compete with ncsim. I don't see Cadence driving
verilog at the expense of all else, rather just happy to see sales. If I
limit 'EDA' to just sim, then I'm not sure Mentor is that far out of
it.  I suspect mixed mode is growing, and Synopsys are a touch out of it
there. 


> The OP was asking about 
> Verilog vs. VHDL, and I was pointing out that the opinions on this 
> question were generally formed not by engineers, but by the people who 
> own the EDA industry: ie. basically Cadence and Synopsys. One thing that 
> strikes me is that engineers are very quick to complain when Microsoft 
> tries to form public opinion, but generally don't even notice when the 
> same thing happens in the EDA industry.
> 

I'd opine instead thet VHDL may be more driven by FPGA and academic 
interests than by the EDA companies. Possibly some good relationships
forged by Nodeltech here too. 
Not sure any of the EDA companies have demonstrated Microsoft's skill
with lock-in though. I can list IEEE specs for verilog and vhdl if I
really try..



>  However, the OP wasn't doing gate-level 
> modelling, and this is only one factor out of maybe 20 or 30 that you 
> would have to evaluate if you were seriously comparing VHDL and Verilog.
> 

This is certainly true. If you know specifically what matters to you,
then a language selection is much easier.

Lets just say both of these languages are real - and there are MANY
successful projects with each. Often the selection does not relate to 
the specific language technical merits.

I know which I personally prefer - but for reasons which probably 
are more  to do with my history that anything else....

[general recommendation] If you are not at least a little conversant
with both - how should you judge?


john




> Evan Lavelle
-- 
John Sheahan <jrsheahan@optushome.com.au>