Re: gEDA-user: VHDL Compiler

[Bill Cox <bill@viasic.com>]

John Sheahan wrote:

> > Synopsys started life with DC, around 1988. Back then, the tool flow was 
> > Verilog-XL (Gateway, Cadence) for simulation, DC for synthesis. Synopsys 
> > didn't need a simulator. They did move into VHDL, both for simulation 
> > and synthesis. However, I think it's always been clear that they would 
> > much rather that there was no VHDL, but it's taken Aart de Geus until 
> > this year to actually say it publicly.
> >
> >    
> possibly. I suspect there was a window there where Synopsys would have
> been thrilled if VHDL and (ie VSS and the appropriate DC reader)  could 
> have killed verilog championed by their main competitor at the time. 
> However VSS was not competitive enough against XL.
...

> I'd opine instead thet VHDL may be more driven by FPGA and academic 
> interests than by the EDA companies. Possibly some good relationships
> forged by Nodeltech here too. 
> Not sure any of the EDA companies have demonstrated Microsoft's skill
> with lock-in though. I can list IEEE specs for verilog and vhdl if I
> really try..
>  
Synopsys was a major force in pushing VHDL early on.  They saw a closed 
Verilog from Cadence as a barrier they couldn't overcome.  The other 
driver was the military, who wanted a clean documentation language that 
would apply at the system level.  FPGA users tend to be VHDL users, 
mostly for two reasons.  First, they learned HDL later than the ASIC 
guys, during the period that Synopsys was pushing VHDL as a replacement 
for Verilog.  Second, the Europeans seem to have a stronger preference 
for US military backed standards than we do here in the US (perhaps this 
is changing?).  Assuming the mix hasn't changed much (a pretty safe 
assumption... few people ever switch HDLs unless forced), in Europe, 
VHDL is the FPGA language of choice.  In the US, it's about 
half-and-half.  In Japan, they prefer Verilog.  Apparently, in Japan 
they prefer to keep using what has worked well in the past.

ASIC guys, on the other hand, had to learn Verilog.  VHDL wasn't ready 
by the time ASICs were too large for schematic capture.  Throw in the 
fact the Verilog tends to simulate faster, and the flattened netlists 
tend to be smaller (neither is a problem for FPGAs), and you get the 
situation where ASIC designers are big on Verilog.

From my point of view, the sad part about this whole mess is the huge 
waste of development resources.  Cadence clearly is at fault for keeping 
Verilog closed for too long.  Having to write all our tools twice, and 
for very little gain in functionality, is tragic.  The EDA industry and 
users would have been far better off  if those resources had been spent 
on new functionality.

Another tragic situation is that now we have trouble sharing HDL code. 
Just go to open-cores.  It's half in Verilog, and half in VHDL.  That 
makes about half the cores useful to any given group, as most of us 
still prefer to avoid mixed language design when possible.

If I had a magic wand, I'd fix the situation by forcing all VHDL guys to 
convert to Verilog.  IMO, that's slightly preferable to the other way 
around, for a variety of reasons that have already been discussed.  If I 
had that wand, I'd fix the messed up spelling in English while I was at 
it, too.  Oh, well...

Bill