Re: gEDA-user: fpga

[Carl Witty <cwitty@xxxxxxxxxxxxxx>]

On Tue, 2005-11-01 at 19:07 -0600, David Hart wrote:
> Though not a GNU project, the JHDL Project is an OpenSource project.
> >From their web site at:
> 
>     http://www.jhdl.org/overview.html
> 
> there is this short teaser about JHDL:
> 
>         Simply put, JHDL is a structurally based Hardware Description
>         Language (HDL) implemented with JAVA.
>         
>         Available appendages to the JHDL circuit model include a set of
>         tools for debugging, simulating, testing and interfacing to the
>         circuit, both as it exists in simulation ("in software",) and
>         while the program is executing on an FPGA ("in hardware.")
>         
>         In its current state JHDL includes:
>         * a library that supports Xilinx 4K, Virtex, and Virtex II
>         series devices.
> 
> I'd be interested in your assessment of this tool. I haven't used it yet
> myself, but it looks to be a great tool for looking into FPGA
> technology.

I like JHDL very much (and have used it for several projects).  As
others have mentioned, JHDL is not a complete solution; you still need
the "free beer" Xilinx tools (currently, I use the Windows version of
Webpack ISE and run it under Wine).  JHDL is used in the "front end" of
the project, where you might otherwise use VHDL, Verilog, or schematic
capture.

JHDL is a Java library for generating EDIF netlists.  In its simplest
form, you can write the same sort of program in JHDL that you could in
(structural) VHDL or Verilog.  However, you also have the full power of
Java available.  Some of the things I've done with JHDL which I think
would be difficult with VHDL or Verilog include:
* For an FPGA which is intended as a CPU peripheral, make it trivial
  to add new registers.  To add a new output register, I type:
     ios.alloc_out_port("uart_send", 8)
  and a new input register is:
     ios.alloc_in("uart_recv", uart_recv)
  The same program that generates the EDIF netlist also generates a C
  header file with register definitions; when I change the JHDL to
  add a new register, a single "make" rebuilds the bitstream and
  recompiles the C code to use the new register numbers.
* For an FPGA which includes a microcontroller, write an assembler for
  the microcontroller in Java.  The same program that generates the
  EDIF netlist assembles the microcontroller code and injects the
  machine code into the EDIF.

However, JHDL does have some disadvantages.  Since it's a Java library,
it's a bit verbose; for instance, where Verilog and VHDL let you use
"+", JHDL makes you use "add(_,_)" (since Java does not have operator
overloading).

Carl Witty