Re: gEDA-user: Spartan3 FT256 layout in PCB

[Darrell Harmon <mail@xxxxxxxxxxxx>]

On Fri, Nov 11, 2005 at 01:03:03PM -0800, Larry Doolittle wrote:
> Friends -
> 
> I took a whack at laying out a Xilinx Spartan3-FT256 in PCB.
> I posted my results so far at
>   http://recycle.lbl.gov/~ldoolitt/ft256/
> It's set up for a 6-layer board, and routes all 184
> non-power pads out to traces on a 0.5 mm grid.
> 
> I welcome constructive criticism, especially in the
> context of (relatively) high speed design.  My interest
> in this chip is for designs running at about 100 MHz.
> 
>    - Larry

Nice job routing out all the signals.

How about taking the power layer under the center as VCCINT.
A strip of plane ran from that to the regulator. VCCAUX had
a plane consuming the rest of the room under the FPGA. That 
would eliminate two of your "Bad points" list. However, you
still have to deal with the VCCO. That could be a mess if you
have too many IO voltages. I did use 20 0402 caps, but I 
suspect that was unnecessary. They fit much better than 0603s
so I could get them closer, but they are hard to solder. I
put up a PDF of the board I did, and can email you pcb files
if you like. It is at http://dlharmon.com/dspcard/dspcard-art.pdf


Darrell Harmon
http://dlharmon.com/dspcard