Re: gEDA-user: wxPCB Goals

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

My four big wishes have been, better bus hierarchy (gaff issue which I
roll my own as mentioned earlier), more then 8 layers (colors not being
maintained for layers greater then 8 the biggest bug at the moment but
it is usable), back annotation and being able to have a better
representation of hierarchy on the fab (areas having reference ids so
that individual components can retain a smaller reference id).

Since gaf and pcb are tool centric as opposed to data centric there is
no expectation for the two to understand the internal data structures or
project file structures other then those that the two need to
communicate netlists and changes to netlists back and forth.

In-deed for back annotation pcb needs to know which gates can be swapped
and which pins (often io pins of fpgas) can be swapped. I believe this
info should be part of the net list that the schematic capture program
generates.

pcb should then generate a report which tells which gates and pins were
swapped. The schematic capture program should then read this in and
change the labels inside the schematic automatically.

What I have to do currently is.... create the schematic, generate the
netlist, load the netlist into pcb... figure out what needs to be
swapped.. modify the schematic... regenerate the netlist... re-import
the netlist into pcb and repeat the proceeding actions many many many
many many times... The biggest pain is often how long it takes to
generate the netlist.

I would like to be able to select a pin and have a list of either what
gates it and associated pins can be swapped for or a list of what pins
an io pin can be swapped for. The user would then select the pin/gate
from the list and pcb would modify the netlist and add the action into
the back annotation file.

With this implace, my activities would change to... create the
schematic, generate the netlist, load the netlist into pcb, lay the
board out swapping gates and pins as needed, load the back annotation
into gschem and automattically shuffle pin and gate labels around to
match the board. The hudge differences are, I am not constantly edditing
a symbol in gschem and regenerating netlists.

I look forward to this being inplace sometime before the middle of the
next decade.

Wishfully thinking,

Steve Meier

On Wed, 2005-11-30 at 07:40 -0500, Dan McMahill wrote:
> Bob Paddock wrote:
> 
> > * Designator renumbering and back-annotation to gschem files.
> 
> I have some thoughts about the back-annotation bit.  It would be nice to 
> avoid pcb and gschem needing to know too much about each others internal 
> file formats.
> 
> > * BOM generator.
> 
> is this different than the one which is already in pcb?
> 
> -Dan
>