Re: gEDA-user: Schematic Level DRC DIscussion

[John Doty <jpd@xxxxxxxxxxxxx>]

On Nov 6, 2007, at 1:04 PM, Steve Meier wrote:

> U1
>
> pin  1   "D1"  pas
> pin  2   "NC"  pas
> pin  3   "D3"  pas
> pin  4   "S3"  pas
> pin  5   "S4"  pas
> pin  6   "D4"  pas
> pin  7   "NC"  pas
> pin  8   "D2"  pas
> pin  9   "S2"  pas
> pin 10   "IN2"  in
> pin 11   "V+"  pwr
> pin 12   "VL"  pwr
> pin 13   "GND" pwr
> pin 14   "V-"  pwr
> pin 15   "IN1"  in
> pin 16   "S1"  pas
>
>
> J1  pins are   pas

Yes. But does that really make sense?

>
> nets:
>
> U1.1 U1.3 U1.4 U1.5 U1.6 U1.8 J1.A4
> U1.9 U1.10 U1.11 U1.12 U1.13 U1.14 U1.15 J1.B3
> U1.16 J1.A4
>
>
> First:  J1.A4 is used twice in effect reducing the nets to two nets

Yes. Is that a real error? I think it is right now, but should  
gnetlist treat these as separate nets? It doesn't for a ground  
symbol, for example.

>
> U1.1 U1.3 U1.4 U1.5 U1.6 U1.8 U1.16 J1.A4           All pins pas
> U1.9 U1.10 U1.11 U1.12 U1.13 U1.14 U1.15 J1.B3      pins include types
> such as pas, in and pwr
>
>
> For the second net arcording to the drc2 matrix
>
> 1) pas may connect to pas, in or pwr
> 2) in may connect to in or pwr
>
> There for DRC2 thinks that there are no connection errors.

Yes. Those rules are almost useless in mixed signal circuits.

>
>> From my reading of DRC2 it tests for
>
> 1) Non numbered parts
> 2) Duplicate references

But, of course, some of us often use multiple symbols for one part.

> 3) One connection nets

That's somewhat useful. But it also complains of unconnected pins,  
which are normal, not usually errors.

> 4) net pin types

Using a classification nearly irrelevant to anything except pure  
digital design.

> 5) slots
> 6) duplicated slots
> 7) un-used slots
>
> I would expect complaints about duplicate slots and un-used slots.

Unused connector pins are extremely common in error-free designs. And  
I think it adds clarity to treat connectors as multi-slot rather than  
having a lot of named lines converging on a big block.

> Not
> about the way the pins are hooked together. One obvious weakness is  
> that
> the test schematic connects, V+, V-, VL and GND together. These are  
> all
> type pwr and thus according to the matrix they may be connected. I  
> think
> this is a weakness of pins not being heavier.

Yes, but how to fix. Making the pins heavier will make symbol  
construction even harder for new users. Pin classification is already  
confusing.

>
> Steve Meier
>
> On Tue, 2007-11-06 at 09:36 -0700, John Doty wrote:
>> On Nov 6, 2007, at 7:27 AM, Steve Meier wrote:
>>
>>> What do we expect the schematic DRC to catch?
>>>
>>> 1) Detect duplicate use of reference designators, but don't
>>> complain if
>>> the usage is for different slots.
>>> 2) For a multi-symbol device check to make sure that the pins arn't
>>> used
>>> multiple times?
>>
>> Is that an error?
>>
>>>
>>> But what else and what are the implications for heavy/light symbols?
>>
>> Here's a simple schematic, with a silly useless circuit, many
>> problems. It provokes *numerous* drc2 errors and warnings, but only
>> two of them are real mistakes. And arguably, one should be able to
>> duplicate connector pins for clarity within the schematic, although
>> right now such usage doesn't netlist correctly. But drc2 misses all
>> of the intentional errors.
>>
>>>
>>> Steve Meier
>>>
>>>
>>> _______________________________________________
>>> geda-user mailing list
>>> geda-user@xxxxxxxxxxxxxx
>>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>>
>> John Doty              Noqsi Aerospace, Ltd.
>> http://www.noqsi.com/
>> jpd@xxxxxxxxx
>>
>>
>>
>> _______________________________________________
>> geda-user mailing list
>> geda-user@xxxxxxxxxxxxxx
>> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>
>
>
> _______________________________________________
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John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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