gEDA-user: Can't get outline layer working

[Christian Gagneraud <cgagneraud@xxxxxxxxxxxx>]

Hi all,

I have followed some thread in the mailing list archive about outline
layer within pcb but...

So i have added a layer named "outline", i drawn a rectangle on it with
10mil line thickness, but now when i export as ps or even gerber, pcb
doesn't take my outline specification into account. Instead it outputs a
board as big as defined in the "PCB[..]" line stuff.
Even the "disperse" function, place my components outside these limits.

I'm using PCB version 20070912.

Here is my file (this is an "empty" pcb, which i would like to use as a
template, it defines the size of the board, a convenient screen size,
and 4 vias that are used for screwing the boards), (i have removed lot
of the initial layers because these boards will use only 2 layers):
-------------------------------------------------------
# release: pcb 20070912
# date:    Mon Nov 12 17:14:26 2007
# user:    cgagneraud (Christian Gagneraud)
# host:    xxx.techworks.ie

# To read pcb files, the pcb version (or the cvs source date) must be >=
the file version
FileVersion[20070407]

PCB["Please go to Edit->Edit name of->layout" 629921 590551]

Grid[1000.000000 0 0 1]
Cursor[0 0 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[2000 2000 2000 1000 3150 3150]
Flags("showdrc,nameonpcb,clearnew")
Groups("1,c:2,s:3:4")
Styles["Signal,2000,6000,3000,2000:Power,2500,6000,3000,2500:Fat,4000,8000,4000,2500:Skinny,1000,3000,1500,1000"]
[ ... Symbol ...]
Via[120015 119995 25600 2000 0 12000 "" "lock"]
Via[120015 473995 25600 2000 0 12000 "" "lock"]
Via[513015 473995 25600 2000 0 12000 "" "lock"]
Via[513015 119995 25600 2000 0 12000 "" "lock"]
Layer(1 "component")
(
)
Layer(2 "solder")
(
)
Layer(3 "outline")
(
        Line[100000 100000 100000 494000 1000 2000 "clearline,lock"]
        Line[100000 494000 533000 494000 1000 2000 "clearline,lock"]
        Line[533000 494000 533000 100000 1000 2000 "clearline,lock"]
        Line[533000 100000 100000 100000 1000 2000 "clearline,lock"]
)
Layer(4 "silk")
(
)
Layer(5 "silk")
(
)
-------------------------------------------------------

I am wondering if i need a more recent version of PCB (from CVS?), or
perhaps am i missing something around, if so can anyone gives me some
tips/advice?

Thanks in advance,
Krys




-- 
Christian Gagneraud <cgagneraud@xxxxxxxxxxxx>
TechWorks Marine



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