Re: gEDA-user: Problem with OGD1: Can anyone advise on good low-jitter

["a r" <nbs.public@xxxxxxxxx>]

Random ideas: try better supply decoupling or package, stop other FPGA
outputs when the clock generator is active (or at least put them far
from the generator outputs). Check PCB - especially for return current
paths of noisy signals.

 -r.

On Nov 28, 2007 7:09 PM, Timothy Normand Miller <theosib@xxxxxxxxx> wrote:
> Sorry about the cross-post.  We're -><- THIS close to getting OGD1
> done, with artwork in the hands of board makers who are working on
> quotes, and we've discovered a problem that could make the video
> output unacceptable.
>
> We've discovered that the clock generators in the Xilinx FPGA part are
> lousy for generating video clocks.  We're seeing like 900ps of jitter,
> which causes artifacts on DVI monitors at resolutions as low as
> 1280x1024 when the cable gets beyond a certain length.  (I don't
> recall all the details.)
>
> One option is to use the clock generators in the Lattice part, but
> even they have like 400ps of jitter, and they also severely limit the
> range of frequencies we can generate.
>
> So the best solution we can come up with is to put on some external
> clock generators.  One for each video head.  Problems:  (1) more time
> to mod the design, (2) up to $15 each for the generators, (3) we have
> no idea what generators to use, how good they are, how to wire them.
>
> Does anyone know anything about these?  Do you have experience with
> specific high-frequency clock generators and know how they perform and
> what kind of jitter they produce?
>
> Unfortunately, it could take quite a long time for us to find
> suppliers of clock generators, get samples, wire them up and test
> them, etc., so we just need find out if someone out there already has
> the right answer or knows where to look for it.
>
> Thank you for your time!
>
> --
> Timothy Normand Miller
> http://www.cse.ohio-state.edu/~millerti
> Open Graphics Project
>
>
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