gEDA-user: PCB+GL notes on VBOs

[Peter Clifton <pcjc2@xxxxxxxxx>]

(Sorry for the incomplete send before)

Notes:

1. VBOs should be fast. As fast, or faster than plain vertex arrays.
2. I came to this conclusion having read the Intel driver code.. vertex 
   arrays use _EXACTLY_ the same mapping and upload paths as VBOs ;)
3. My code seems to be faster with vertex arrays - why..

Lots of stupid reasons:

1. My VBOs and arrays are pretty large buffers, to fit lots of geometry.

2. The buffer size is mismatched to the average glDrawArrays call, as we
   often have to dispatch early due to other state-changes such as 
   colour or grouping sub-composited layers.

3. The buffer size is overly large now that I'm using pixel shaders for
   much of the rounded geometry like line caps. We're not seeing the
   full benefit of that reduced geometric complexity yet if it doesn't
   reflect in the upload bandwidth used. (Not such an issue with 
   properly mapped buffers on integrated graphics chips though).

4. Unfortunately, my polygon code is fairly dumb, and wants to dispatch
   and entire contour at once. Currently I need a large buffer in case
   we hit a complex polygon. (I kept bumping the size up as I found
   bigger and bigger boards which could expend the buffer). I need to 
   fix for robustness, and also - it could help tune VBO sizes.


So.. we have a large buffer. That is a large chunk of graphics memory to
be requesting all the time. I think that contributes if the card doesn't
have a decent chunk free yet.

If we fall back to glBufferData / glBufferSubData (in the dumb way my
code was calling it at least), we copy a huge buffer just to draw the
first "N" elements from it - I will go fix that now ;) Bad Peter!

Other than this, I don't know why glMapBuffer() doesn't "just work"
performantly (after using glBufferData(..., NULL) to discard the
previous data). The only penalty ought to be allocating card / driver
memory, and this ought to happen in a ring like fashion from identically
sized areas we've previously completed rendering from.


-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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