Re: gEDA-user: DRC check workaround for outline layer

[Kovacs Levente <leventelist@xxxxxxxxx>]

On Tue, 23 Nov 2010 15:56:39 +0000
Peter Clifton <pcjc2@xxxxxxxxx> wrote:

> This is probably not something we'd commit as is to PCB, as for some
> cases, DRC warnings on the outline layer could be useful, but Bdale
> was looking for something along these lines on IRC yesterday.

I'd love to see that patch in HEAD. Or maybe that version, which looks for
layer attributes.

Levente

-- 
Kovacs Levente <leventelist@xxxxxxxxx>
Voice: +36705071002




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